US6890812B2
Expired / Lapsed
US
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Method of forming a memory having a vertical transistor
Assignee: Micron Technology Inc
•
Filing: 2002-12-11
•
Granted: 2005-05-10
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Expires: 2022-12-11
Abstract
Abstract Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. In each memory cell a single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions, and a gate opposing the vertical body region and separated therefrom by a gate oxide. A plurality of buried bit lines are formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells. Also, a plurality of word lines are included. Each word line is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.
Inventors
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:46
CPC Classifications
H; H10; H10B; H10B12/00; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6728; H10B12/01; H10B12/02; H10B12/05; H10B12/053; H10B12/30; H10B12/34; H10D30/01; H10D30/021; H10D30/025; H10D30/63; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10B12/31; H10B12/315; H10B12/48; H10B12/482; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
239 words
A method for forming a memory cell, comprising: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a single crystalline vertical transistor along side of the pillar, wherein forming the single crystalline vertical transistor includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; forming a gate opposing the single crystalline vertically oriented material of the second conductivity type; and forming a capacitor coupled to the second contact layer.
Claim 2
Independent Claim
239 words
A method for forming a memory cell, comprising: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a single crystalline vertical transistor along side of the pillar, wherein forming the single crystalline vertical transistor includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; forming a gate opposing the single crystalline vertically oriented material of the second conductivity type; and forming a capacitor coupled to the second contact layer.
Claim 3
Dependent Claim
44 words
The method of claim 1 , wherein forming a single crystalline vertical transistor along side of the pillar includes forming the transistor such that the transistor has an ultra thin single crystalline vertical body region having a horizontal width of less than 10 nanometers.
Claim 4
Dependent Claim
62 words
The method of claim 1 , wherein forming a single crystalline vertical transistor along side of the pillar includes forming the transistor such that the transistor has a vertical channel length of less than 100 nanometers and has a first and a second source/drain regions wherein the first and the second source/drain regions have a horizontal width of less than 10 nanometers.
Claim 5
Independent Claim
292 words
A method for forming a memory cell, comprising: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a single crystalline vertical transistor along side of the pillar, wherein forming the single crystalline vertical transistor includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; and forming a gate opposing the single crystalline vertically oriented material of the second conductivity type and separated therefrom by a gate oxide; forming a buried bit line of single crystalline semiconductor material below the pillar and coupled to the first contact layer; forming a capacitor coupled to the second contact layer; and forming a word line disposed orthogonally to the buried bit line in a trench below a top surface of the pillar for addressing the gate.
Claim 6
Independent Claim
292 words
A method for forming a memory cell, comprising: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a single crystalline vertical transistor along side of the pillar, wherein forming the single crystalline vertical transistor includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; and forming a gate opposing the single crystalline vertically oriented material of the second conductivity type and separated therefrom by a gate oxide; forming a buried bit line of single crystalline semiconductor material below the pillar and coupled to the first contact layer; forming a capacitor coupled to the second contact layer; and forming a word line disposed orthogonally to the buried bit line in a trench below a top surface of the pillar for addressing the gate.
Claim 7
Dependent Claim
37 words
The method of claim 4 , wherein forming the buried bit line includes forming a buried bit line which is more heavily doped than the first contact layer and is formed integrally with the first contact layer.
Claim 8
Dependent Claim
48 words
The method of claim 4 , wherein forming a single crystalline vertical transistor along side of the pillar includes forming the transistor such that the transistor has the ultra thin single crystalline vertical body region with a p-type channel having a vertical length of less than 100 nanometers.
Claim 9
Dependent Claim
43 words
The method of claim 6 , wherein forming the transistor such that the transistor has the ultra thin single crystalline vertical body region includes forming the ultra thin single crystalline vertical body region to have a horizontal width of less than 10 nanometers.
Claim 10
Dependent Claim
37 words
The method of claim 4 , wherein forming a buried bit line of single crystalline semiconductor material below the pillar includes forming a buried bit line which is separated from the semiconductor substrate by an insulator layer.
Claim 11
Dependent Claim
33 words
The method of claim 4 , wherein forming the gate includes forming a horizontally oriented gate, wherein a vertical side of the horizontally oriented gate has a length of less than 100 nanometers.
Claim 12
Dependent Claim
25 words
The method of claim 4 , wherein forming the gate includes forming a vertically oriented gate having a vertical length of less than 100 nanometers.
Claim 13
Independent Claim
362 words
A method for forming an open bit line DRAM device, comprising: forming an array of memory cells, wherein forming each memory cell in the array of memory cells includes: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a single crystalline vertical transistor along side of the pillar, wherein forming the single crystalline vertical transistor includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; and forming a gate opposing the single crystalline vertically oriented material of the second conductivity type and separated therefrom by a gate oxide; forming a plurality of buried bit lines of single crystalline semiconductor material disposed below the pillars in the array of memory cells such that each one of the plurality of buried bit lines couples the first contact layer of column adjacent pillars in the array of memory cells; and forming a plurality of word lines disposed orthogonally to the plurality of buried bit lines, wherein forming the plurality of word lines includes forming each one of the plurality of word lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.
Claim 14
Independent Claim
362 words
A method for forming an open bit line DRAM device, comprising: forming an array of memory cells, wherein forming each memory cell in the array of memory cells includes: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a single crystalline vertical transistor along side of the pillar, wherein forming the single crystalline vertical transistor includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; and forming a gate opposing the single crystalline vertically oriented material of the second conductivity type and separated therefrom by a gate oxide; forming a plurality of buried bit lines of single crystalline semiconductor material disposed below the pillars in the array of memory cells such that each one of the plurality of buried bit lines couples the first contact layer of column adjacent pillars in the array of memory cells; and forming a plurality of word lines disposed orthogonally to the plurality of buried bit lines, wherein forming the plurality of word lines includes forming each one of the plurality of word lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.
Claim 15
Dependent Claim
42 words
The method of claim 11 , wherein forming each single crystalline vertical transistor includes forming an ultra thin body region with a p-type channel having a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.
Claim 16
Dependent Claim
31 words
The method of claim 11 , wherein forming the plurality of buried bit lines includes forming the plurality of buried bit lines separated by an oxide layer from the semiconductor substrate.
Claim 17
Dependent Claim
67 words
The method of claim 11 , wherein forming the plurality of word lines includes integrally forming each gate along a row of pillars with one of the plurality of word lines in the adjacent trench, and wherein forming each of the plurality of word lines includes forming a horizontally oriented word line having a vertical side of less than 100 nanometers opposing the single crystalline vertical transistor.
Claim 18
Dependent Claim
61 words
The method of claim 11 , wherein forming the plurality of word lines includes integrally forming each gate along a row of pillars with one of the plurality of word lines in the adjacent trench, and wherein forming each of the plurality of word lines includes forming a vertically oriented word line having a vertical length of less than 100 nanometers.
Claim 19
Dependent Claim
41 words
The method of claim 11 , wherein forming the plurality of word lines includes forming the plurality of word lines such that each word line addresses gates for the single crystalline vertical transistors which are both column adjacent and row adjacent.
Claim 20
Independent Claim
425 words
A method of forming a memory device, comprising: forming an array of memory cells, wherein forming each memory cell in the array of memory cells includes: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a pair of single crystalline vertical transistors along opposing sides of the pillar, wherein forming each one of the pair of single crystalline vertical transistors includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on opposing sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; and forming a pair of gates, each gate opposing the single crystalline vertically oriented material of the second conductivity type and separated therefrom by a gate oxide; forming a plurality of buried bit lines of single crystalline semiconductor material disposed below the pillars in the array of memory cells such that each one of the plurality of buried bit lines couples the first contact layer of column adjacent pillars in the array of memory cells; and forming a plurality of first word lines disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to a first side of the trench; and forming a plurality of second word lines disposed orthogonally to the bit lines in the trench between rows of the pillars and separated from each first word line by an insulator such that the second word line is adjacent a second side of the trench and addresses gates of the single crystalline vertical transistors that are adjacent to a second side of the trench.
Claim 21
Independent Claim
425 words
A method of forming a memory device, comprising: forming an array of memory cells, wherein forming each memory cell in the array of memory cells includes: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a pair of single crystalline vertical transistors along opposing sides of the pillar, wherein forming each one of the pair of single crystalline vertical transistors includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on opposing sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; and forming a pair of gates, each gate opposing the single crystalline vertically oriented material of the second conductivity type and separated therefrom by a gate oxide; forming a plurality of buried bit lines of single crystalline semiconductor material disposed below the pillars in the array of memory cells such that each one of the plurality of buried bit lines couples the first contact layer of column adjacent pillars in the array of memory cells; and forming a plurality of first word lines disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to a first side of the trench; and forming a plurality of second word lines disposed orthogonally to the bit lines in the trench between rows of the pillars and separated from each first word line by an insulator such that the second word line is adjacent a second side of the trench and addresses gates of the single crystalline vertical transistors that are adjacent to a second side of the trench.
Claim 22
Dependent Claim
91 words
The method of claim 17 , wherein forming the plurality of first word lines includes integrally forming each gate along a row of pillars adjacent a first side of the trench with one of the plurality of the first word lines adjacent the first side of the trench, and wherein forming the plurality of second word lines includes integrally forming each gate along a row of pillars adjacent a second side of the trench with one of the plurality of the second word lines adjacent the second side of the trench.
Claim 23
Dependent Claim
33 words
The method of claim 18 , wherein forming each of the plurality of first and second word lines includes forming vertically oriented word lines having a vertical length of less than 100 nanometers.
Claim 24
Dependent Claim
39 words
The method of claim 18 , wherein forming each single crystalline vertical transistor includes forming the single crystalline vertical transistor to have a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.
Claim 25
Independent Claim
107 words
A method of forming a memory cell, comprising: forming a pillar extending outwardly from a substrate, including forming a first contact layer, forming an insulator on the first contact layer, and forming a second contact layer on the insulator; forming a vertical transistor along a side of the pillar, wherein the vertical transistor has a body region with a vertical length of less than 100 nm in which a vertical channel region is formed, and further has both a first source/drain region and a second source/drain region which have a scalable junction depth less than 10 nm; and forming a capacitor coupled to the second contact layer.
Claim 26
Independent Claim
107 words
A method of forming a memory cell, comprising: forming a pillar extending outwardly from a substrate, including forming a first contact layer, forming an insulator on the first contact layer, and forming a second contact layer on the insulator; forming a vertical transistor along a side of the pillar, wherein the vertical transistor has a body region with a vertical length of less than 100 nm in which a vertical channel region is formed, and further has both a first source/drain region and a second source/drain region which have a scalable junction depth less than 10 nm; and forming a capacitor coupled to the second contact layer.
Claim 27
Dependent Claim
117 words
The method of claim 21 , wherein: forming a first contact layer includes forming a single crystalline first contact layer of a first conductivity type, and forming a second contact layer includes forming a single crystalline second contact layer of the first conductivity type; and forming a vertical transistor along a side of the pillar includes: forming a lightly doped polysilicon layer along the side of the pillar; and annealing the pillar to: recrystallize the lightly doped polysilicon layer and form a single crystalline vertically-oriented material of the second conductivity type; and form vertically-oriented first and second source/drain regions of the first conductivity type separated by the single crystalline vertically oriented material of the second conductivity type.
Claim 28
Dependent Claim
56 words
The method of claim 22 , wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer to form the vertically-oriented first and second source/drain regions of the first conductivity type.
Claim 29
Dependent Claim
39 words
The method of claim 21 , wherein: forming the first contact layer includes forming the first contact layer to couple to a buried bit line; and the method further comprising forming a word line to gate the vertical transistor.
Claim 30
Dependent Claim
16 words
The method of claim 21 , wherein forming the insulator layer includes forming an oxide layer.
Claim 31
Independent Claim
90 words
A method of forming a memory cell, comprising: forming a pillar extending outwardly from a substrate, including forming a single crystalline first contact layer of a first conductivity type, forming an insulator on the first contact layer, and forming a single crystalline second contact layer of the first conductivity type on the insulator; forming a vertical transistor along a side of the pillar, including forming a lightly doped polysilicon layer along the side of the pillar, and annealing the pillar; and forming a capacitor coupled to the second contact layer.
Claim 32
Independent Claim
90 words
A method of forming a memory cell, comprising: forming a pillar extending outwardly from a substrate, including forming a single crystalline first contact layer of a first conductivity type, forming an insulator on the first contact layer, and forming a single crystalline second contact layer of the first conductivity type on the insulator; forming a vertical transistor along a side of the pillar, including forming a lightly doped polysilicon layer along the side of the pillar, and annealing the pillar; and forming a capacitor coupled to the second contact layer.
Claim 33
Dependent Claim
52 words
The method of claim 26 , wherein the vertical transistor has a body region with a vertical length of less than 100 nm in which a vertical channel region is formed, and both a first source/drain region and a second source/drain region which have a scalable junction depth less than 10 nm.
Claim 34
Dependent Claim
56 words
The method of claim 26 , wherein annealing the pillar recrystallizes the lightly doped polysilicon layer and forms a single crystalline vertically oriented material of the second conductivity type, and forms vertically oriented first and second source/drain regions of the first conductivity type separated by the single crystalline vertically oriented material of the second conductivity type.
Claim 35
Dependent Claim
39 words
The method of claim 26 , wherein: forming the first contact layer includes forming the first contact layer to couple to a buried bit line; and the method further comprising forming a word line to gate the vertical transistor.
Claim 36
Independent Claim
132 words
A method of forming a memory cell, comprising: forming a pillar extending outwardly from a substrate, including forming a single crystalline first contact layer of a first conductivity type, forming an insulator on the first contact layer, and forming a single crystalline second contact layer of the first conductivity type on the insulator; forming a vertical transistor along a side of the pillar, including: forming a lightly doped polysilicon layer along the side of the pillar; recrystallizing the lightly doped polysilicon layer to form a single crystalline vertically oriented material of the second conductivity type; and forming vertically oriented first and second source/drain regions of the first conductivity type separated by the single crystalline vertically oriented material of the second conductivity type; and forming a capacitor coupled to the second contact layer.
Claim 37
Independent Claim
132 words
A method of forming a memory cell, comprising: forming a pillar extending outwardly from a substrate, including forming a single crystalline first contact layer of a first conductivity type, forming an insulator on the first contact layer, and forming a single crystalline second contact layer of the first conductivity type on the insulator; forming a vertical transistor along a side of the pillar, including: forming a lightly doped polysilicon layer along the side of the pillar; recrystallizing the lightly doped polysilicon layer to form a single crystalline vertically oriented material of the second conductivity type; and forming vertically oriented first and second source/drain regions of the first conductivity type separated by the single crystalline vertically oriented material of the second conductivity type; and forming a capacitor coupled to the second contact layer.
Claim 38
Dependent Claim
52 words
The method of claim 30 , wherein the vertical transistor has a body region with a vertical length of less than 100 nm in which a vertical channel region is formed, and both a first source/drain region and a second source/drain region which have a scalable junction depth less than 10 nm.
Claim 39
Dependent Claim
97 words
The method of claim 30 , wherein recrystallizing the lightly doped polysilicon layer and forming vertically oriented first and second source/drain regions of the first conductivity type includes annealing the pillar which causes the single crystalline first and second contact layers of a first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type.
Claim 40
Dependent Claim
39 words
The method of claim 30 , wherein: forming the first contact layer includes forming the first contact layer to couple to a buried bit line; and the method further comprising forming a word line to gate the vertical transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2008-05-09 | 2008-11-08 | 2009-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-05-09 | 2012-11-08 | 2013-05-10 | $3760.00 | Window Closed / Lapsed |
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