US6153468A
Expired / Lapsed
US
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Method of forming a logic array for a decoder
Assignee: Micron Technology Inc
•
Filing: 1999-05-17
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Granted: 2000-11-28
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Expires: 2019-05-17
Abstract
Abstract A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the decoder. The decoder is programmed at memory test to select an output line responsive to the bits received via the address input lines. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. The control lines are formed together with interconnecting address input lines. The source regions share a common ground while the drain regions are connected to the output lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F 2 is needed per bit of logic, where F is the minimum lithographic feature size.
Inventors
- 👤 Leonard Forbes
- 👤 Wendell P. Noble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:57
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C8/00; G11C8/10; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
273 words
A method of forming a logic array for a decoder, the method comprising: forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces; forming a plurality of first source and drain regions, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between a pillar and the substrate; forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first source and drain region; forming a gate dielectric on at least a portion of the side surface of one of the pillars; forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric; forming a plurality of control lines, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between common pillars; forming an intergate dielectric, interposed between the floating gates and the control lines; forming an intergate dielectric, interposed between the two control lines between the common pillars; forming a plurality of address input lines, each address input line interconnecting one of the control lines; forming at least one first source and drain interconnection line interconnecting one of the first source and drain regions; and forming a plurality of data lines, each data line interconnecting one of the second source and drain regions.
Claim 2
Independent Claim
273 words
A method of forming a logic array for a decoder, the method comprising: forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces; forming a plurality of first source and drain regions, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between a pillar and the substrate; forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first source and drain region; forming a gate dielectric on at least a portion of the side surface of one of the pillars; forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric; forming a plurality of control lines, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between common pillars; forming an intergate dielectric, interposed between the floating gates and the control lines; forming an intergate dielectric, interposed between the two control lines between the common pillars; forming a plurality of address input lines, each address input line interconnecting one of the control lines; forming at least one first source and drain interconnection line interconnecting one of the first source and drain regions; and forming a plurality of data lines, each data line interconnecting one of the second source and drain regions.
Claim 3
Dependent Claim
22 words
The method of claim 1, further comprising forming an insulating layer between the semiconductor pillars and a semiconductor portion of the substrate.
Claim 4
Dependent Claim
25 words
The method of claim 1, wherein forming at least one first source and drain interconnection line is carried out at least partially within the substrate.
Claim 5
Dependent Claim
23 words
The method of claim 1, wherein forming the plurality of address input lines includes forming a plurality of substantially parallel address input lines.
Claim 6
Dependent Claim
73 words
The method of claim 1, wherein forming the plurality of pillars further comprises: growing an epitaxial layer on the substrate; etching the epitaxial layer and a portion of the underlying substrate to form a plurality of first troughs therein for carrying an insulator; and etching the epitaxial layer to form therein a plurality of second troughs, substantially orthogonal to the plurality of first troughs, the second troughs for carrying the address input lines.
Claim 7
Dependent Claim
60 words
The method of claim 5, wherein forming the plurality of floating gates comprises: depositing polysilicon in the second troughs; and etching the deposited polysilicon in a median portion of the second troughs to form the floating gates on either side of the second troughs, each floating gate adjacent to one of the pillars but separated therefrom by the gate dielectric.
Claim 8
Dependent Claim
56 words
The method of claim 6, wherein forming the plurality of address input lines comprises: etching into the substrate in a median portion of the second troughs; and depositing conductive polysilicon in and above the substrate in the etched median portion of the second troughs to form the address input lines and one of the floating gates.
Claim 9
Dependent Claim
24 words
The method of claim 1, wherein forming the plurality of second source and drain regions comprises ion-implanting a dopant of the second conductivity type.
Claim 10
Dependent Claim
33 words
The method of claim 1, wherein forming the gate dielectric comprises growing on the side surface of each pillar a layer of silicon dioxide of thickness approximately between 5 nanometers and 10 nanometers.
Claim 11
Dependent Claim
66 words
The method of claim 1, wherein forming the plurality of data lines comprises: depositing an insulator over the pillars, the floating gates, and the address input lines; forming contact holes in the insulator to contact the second source and drain regions of each pillar; depositing a conductive layer on the insulator and in the contact holes; and etching the conductive layer to form the data lines.
Claim 12
Independent Claim
203 words
A method of forming a decoder logic array on a substrate, the method comprising: forming a first source and drain layer at a surface of the substrate; forming a semiconductor epitaxial layer on the first source and drain layer; forming a second source and drain layer at a surface of the epitaxial layer; etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer; forming an insulator in the first troughs; etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer; forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs; forming a conductive layer in the second troughs; removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer; forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs; and forming control line regions between opposing floating gate regions in the second troughs and separated from the floating gate regions in the second troughs by the intergate dielectric layer.
Claim 13
Independent Claim
203 words
A method of forming a decoder logic array on a substrate, the method comprising: forming a first source and drain layer at a surface of the substrate; forming a semiconductor epitaxial layer on the first source and drain layer; forming a second source and drain layer at a surface of the epitaxial layer; etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer; forming an insulator in the first troughs; etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer; forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs; forming a conductive layer in the second troughs; removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer; forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs; and forming control line regions between opposing floating gate regions in the second troughs and separated from the floating gate regions in the second troughs by the intergate dielectric layer.
Claim 14
Dependent Claim
12 words
The method of claim 11, wherein the substrate is a bulk semiconductor.
Claim 15
Dependent Claim
12 words
The method of claim 11, wherein the substrate includes a semiconductor-on-insulator portion.
Claim 16
Dependent Claim
18 words
The method of claim 11, further comprising forming an insulating layer undercutting semiconductor regions between the first troughs.
Claim 17
Independent Claim
211 words
A method of forming a decoder logic array on a substrate, comprising: forming a first source and drain layer at a surface of the substrate; forming a semiconductor epitaxial layer on the first source and drain layer; forming a second source and drain layer at a surface of the epitaxial layer; etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer; forming an insulator in the first troughs; etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer; forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs; forming a conductive layer in the second troughs; removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer; forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs; forming split control line regions between opposing floating gate regions in the second troughs; separating from the floating gate regions in the second troughs by the intergate dielectric layer; and separating the split control lines by the intergate dielectric layer.
Claim 18
Independent Claim
211 words
A method of forming a decoder logic array on a substrate, comprising: forming a first source and drain layer at a surface of the substrate; forming a semiconductor epitaxial layer on the first source and drain layer; forming a second source and drain layer at a surface of the epitaxial layer; etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer; forming an insulator in the first troughs; etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer; forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs; forming a conductive layer in the second troughs; removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer; forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs; forming split control line regions between opposing floating gate regions in the second troughs; separating from the floating gate regions in the second troughs by the intergate dielectric layer; and separating the split control lines by the intergate dielectric layer.
Claim 19
Dependent Claim
12 words
The method of claim 15, wherein the substrate is a bulk semiconductor.
Claim 20
Dependent Claim
12 words
The method of claim 15, wherein the substrate includes a semiconductor-on-insulator portion.
Claim 21
Dependent Claim
18 words
The method of claim 15, further comprising forming an insulating layer undercutting semiconductor regions between the first troughs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |