Patent US4628429A successfully refreshed from Google Patents.
US5963469A
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Vertical bipolar read access for low voltage memory cell
Assignee: Micron Technology Inc
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Filing: 1998-02-24
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Granted: 1999-10-05
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Expires: 2018-02-24
Abstract
Abstract A memory device is described which has an n-channel FET access transistor coupled between a memory cell and a data communication line. An NPN bipolar access transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar access transistor is described as coupled to a body of the n-channel access transistor to control threshold voltage variations of the n-channel FET access transistor. During operation the n-channel FET access transistor is used for writing data to a memory cell, while the NPN bipolar access transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/405; H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/30; H10B12/34
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
72 words
A memory cell access device comprising: an n-channel FET access transistor coupled between a memory cell and a data communication line; and an NPN bipolar access transistor coupled between the memory cell and the data communication line, such that the n-channel access transistor and the NPN bipolar access transistor are connected in parallel, a base connection of the NPN bipolar access transistor is coupled to a body of the n-channel access transistor.
Claim 2
Dependent Claim
72 words
A memory cell access device comprising: an n-channel FET access transistor coupled between a memory cell and a data communication line; and an NPN bipolar access transistor coupled between the memory cell and the data communication line, such that the n-channel access transistor and the NPN bipolar access transistor are connected in parallel, a base connection of the NPN bipolar access transistor is coupled to a body of the n-channel access transistor.
Claim 3
Dependent Claim
25 words
The memory cell access device of claim 1 wherein the n-channel access transistor and the NPN bipolar access transistor are fabricated as a single unit.
Claim 4
Dependent Claim
95 words
The memory cell access device of claim 2 comprising: a first layer of n-type semiconductor material; a p-type semiconductor material fabricated on top of the first layer of n-type semiconductor material; an n-channel FET access transistor gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation; and a second layer of n-type semiconductor material fabricated on top of the p-type semiconductor material, such that the p-type semiconductor material functions as both a body of the n-channel FET access transistor and a base of the NPN bipolar access transistor.
Claim 5
Dependent Claim
40 words
The memory cell access device of claim 3 wherein the p-type semiconductor material has a doping profile such that a bottom portion of the p-type semiconductor material is more heavily doped than a top portion of the p-type semiconductor material.
Claim 6
Dependent Claim
32 words
The memory cell access device of claim 1 wherein the memory cell access device is fabricated in a low voltage memory device receiving a supply voltage which is less than three volts.
Claim 7
Dependent Claim
21 words
The memory cell access device of claim 5 wherein the low voltage memory device is a dynamic random access memory (DRAM).
Claim 8
Dependent Claim
38 words
The memory cell access device of claim 1 wherein the n-channel FET access transistor is used to write date to the memory cell, and the NPN bipolar access transistor is used to read data from the memory cell.
Claim 9
Dependent Claim
78 words
A low voltage memory cell access device fabricated as a vertical pillar structure, the memory cell access device comprising: an FET access transistor coupled between a memory cell and a data communication line; and a bipolar transistor coupled between the memory cell and the data communication line, such that the FET access transistor and the bipolar transistor are connected in parallel, a base connection of the bipolar transistor is coupled to a body of the FET access transistor.
Claim 10
Dependent Claim
78 words
A low voltage memory cell access device fabricated as a vertical pillar structure, the memory cell access device comprising: an FET access transistor coupled between a memory cell and a data communication line; and a bipolar transistor coupled between the memory cell and the data communication line, such that the FET access transistor and the bipolar transistor are connected in parallel, a base connection of the bipolar transistor is coupled to a body of the FET access transistor.
Claim 11
Dependent Claim
27 words
The low voltage memory cell access device of claim 8 wherein the FET access transistor is an N-channel transistor and the bipolar transistor is an NPN transistor.
Claim 12
Dependent Claim
154 words
The low voltage memory cell access device of claim 9 wherein the FET access transistor and the bipolar transistor are fabricated as a common structure comprising: a first layer of n-type semiconductor material; a p-type semiconductor material fabricated on top of the first layer of n-type semiconductor material; an N-channel transistor gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation; and a second layer of n-type semiconductor material fabricated on top of the p-type semiconductor material, such that the first layer of n-type semiconductor material forms an emitter of the NPN transistor and a source of the N-channel transistor, the p-type semiconductor material functions as both a body of the N-channel transistor and a base of the NPN bipolar access transistor, and the second layer of n-type semiconductor material functions as a drain of the N-channel transistor and a collector of the NPN bipolar access transistor.
Claim 13
Dependent Claim
31 words
The low voltage memory cell access device of claim 10 wherein the second layer of n-type semiconductor material is fabricated as a common bit line between a plurality of memory cells.
Claim 14
Dependent Claim
45 words
The low voltage memory cell access device of claim 10 further comprising a first word line coupled to the N-channel transistor gate for activating the N-channel transistor, and a second word line coupled to the p-type semiconductor material for activating the NPN bipolar access transistor.
Claim 15
Dependent Claim
42 words
The low voltage memory cell access device of claim 8 wherein the p-type semiconductor material has a doping profile such that a bottom portion of the p-type semiconductor material is more heavily doped than a top portion of the p-type semiconductor material.
Claim 16
Dependent Claim
25 words
The low voltage memory cell access device of claim 8 wherein the low voltage memory cell access device is fabricated using a silicon-on-insulator (SOI) construction.
Claim 17
Dependent Claim
23 words
The low voltage memory cell access device of claim 8 wherein the low voltage memory cell access device is fabricated in bulk silicon.
Claim 18
Dependent Claim
91 words
A memory device having a low voltage supply, the memory device comprising: a plurality of memory cells; a plurality of data communication bit lines; and a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines, each of the plurality of memory cell access devices comprising: an FET access transistor, and a bipolar access transistor, such that the FET access transistor and the bipolar access transistor are connected in parallel between a memory cell and a data communication bit line.
Claim 19
Dependent Claim
91 words
A memory device having a low voltage supply, the memory device comprising: a plurality of memory cells; a plurality of data communication bit lines; and a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines, each of the plurality of memory cell access devices comprising: an FET access transistor, and a bipolar access transistor, such that the FET access transistor and the bipolar access transistor are connected in parallel between a memory cell and a data communication bit line.
Claim 20
Dependent Claim
19 words
The memory device of claim 16 wherein the low voltage supply is less than or equal to two volts.
Claim 21
Dependent Claim
17 words
The memory device of claim 16 wherein the memory device is a dynamic random access memory (DRAM).
Claim 22
Dependent Claim
24 words
The memory device of claim 16 wherein the FET access transistor is an N-channel transistor and the bipolar access transistor is an NPN transistor.
Claim 23
Dependent Claim
33 words
The memory device of claim 16 further comprising a plurality of current sense amplifier coupled to the plurality of data communication bit lines for sensing data stored on the plurality of memory cell.
Claim 24
Independent Claim
61 words
A method of accessing a memory cell, the method comprising the steps of: activating an FET access transistor coupled between the memory cell and a data communication line for writing data charge to the memory cell; and activating a bipolar access transistor coupled between the memory cell and a data communication line for reading a charge stored on the memory cell.
Claim 25
Independent Claim
61 words
A method of accessing a memory cell, the method comprising the steps of: activating an FET access transistor coupled between the memory cell and a data communication line for writing data charge to the memory cell; and activating a bipolar access transistor coupled between the memory cell and a data communication line for reading a charge stored on the memory cell.
Claim 26
Dependent Claim
23 words
The method of claim 21 wherein the FET access transistor is an N-channel transistor and the bipolar access transistor is an NPN transistor.
Claim 27
Dependent Claim
21 words
The method of claim 22 wherein a body of the N-channel transistor is coupled to a base of the NPN transistor.
Claim 28
Dependent Claim
20 words
The method of claim 23 wherein a gate voltage of the FET access transistor varies between zero and three volts.
Claim 29
Dependent Claim
20 words
The method of claim 23 wherein a base voltage of the NPN access transistor varies between 0.7 and 1.6 volts.
Claim 30
Dependent Claim
23 words
The method of claim 23 wherein the FET access transistor and the bipolar access transistor are fabricated in a common vertical pillar structure.
Claim 31
Dependent Claim
140 words
The method of claim 26 wherein the common vertical pillar structure comprises: a first layer of n-type semiconductor material; a p-type semiconductor material fabricated on top of the first layer of n-type semiconductor material; an N-channel transistor gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation; and a second layer of n-type semiconductor material fabricated on top of the p-type semiconductor material, such that the first layer of n-type semiconductor material forms an emitter of the NPN transistor and a source of the N-channel transistor, the p-type semiconductor material functions as both a body of the N-channel transistor and a base of the NPN bipolar access transistor, and the second layer of n-type semiconductor material functions as a drain of the N-channel transistor and a collector of the NPN bipolar access transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-04 | 2003-04-05 | 2003-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-04 | 2007-04-05 | 2007-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-04 | 2011-04-05 | 2011-10-05 | $7700.00 | Window Closed / Lapsed |