US5504357A
Expired / Lapsed
US
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Dynamic random access memory having a vertical transistor
Assignee: SK Hynix Inc
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Filing: 1994-06-30
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Granted: 1996-04-02
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Expires: 2014-06-30
Abstract
Abstract A DRAM having a vertical transistor of a highly integrated semiconductor device and its manufacturing method are disclosed. A DRAM has a silicon substrate, a word line formed in a silicon substrate, a gate oxide layer formed on the side wall of the word line, a bit line junction region formed on the bottom of a silicon substrate, a bit line that is connected to the a bit line junction region and is insulated from the word line via a first insulating layer, a charge storage electrode junction region formed near the bottom of silicon substrate surface, a pad polysilicon layer that is insulated from the a word line via a second insulating layer and is connected at the top of a charge storage electrode diffusion region, and a charge storage electrode that is connected to the pad polysilicon layer through a contact. Accordingly, a channel region is formed on a silicon substrate positioned on the side wall of a word line by applying the voltage to the word line and thus a signal transmitter is mutually transferred from the bit line to the charge storage electrode.
Inventors
- 👤 Jong S. Kim
- 👤 Hee-Koo Yoon
- 👤 Chung G. Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:19
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/05; H10B12/053; H10B12/34; H10B12/37; H10B12/377; H10B12/48; H10B12/482
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
245 words
A dynamic random access memory having a vertical transistor, comprising: a silicon substrate having an upper surface and having a trench having a bottom surface, a wall surface, and an opening at the upper surface of the silicon substrate; a bit line junction region extending into the silicon substrate from said bottom surface and from a lower region of said wall surface that is adjacent to said bottom surface; a bit fine at said bottom surface of the trench and connected to said bitline junction region; a word line formed in the trench and insulated from said bit line by a first insulating layer, and insulated from the wall surface by a gate oxide layer formed on the wall surface, whereby a vertical channel region is defined in the semiconductor substrate along the gate oxide layer under the word line; a charge storage electrode junction region extending from a region of the wall surface near the opening at the upper surface and connected to said channel region and formed below the surface of said silicon substrate; a pad polysilicon layer connected to the upper part of said charge storage electrode junction region and insulated from said word line via a second insulating layer; a charge storage electrode connected to said pad polysilicon layer, whereby when a voltage is applied to said word line, said vertical channel region is formed so that a signal transmitter is transferred from said bit line to said charge storage electrode.
Claim 2
Dependent Claim
245 words
A dynamic random access memory having a vertical transistor, comprising: a silicon substrate having an upper surface and having a trench having a bottom surface, a wall surface, and an opening at the upper surface of the silicon substrate; a bit line junction region extending into the silicon substrate from said bottom surface and from a lower region of said wall surface that is adjacent to said bottom surface; a bit fine at said bottom surface of the trench and connected to said bitline junction region; a word line formed in the trench and insulated from said bit line by a first insulating layer, and insulated from the wall surface by a gate oxide layer formed on the wall surface, whereby a vertical channel region is defined in the semiconductor substrate along the gate oxide layer under the word line; a charge storage electrode junction region extending from a region of the wall surface near the opening at the upper surface and connected to said channel region and formed below the surface of said silicon substrate; a pad polysilicon layer connected to the upper part of said charge storage electrode junction region and insulated from said word line via a second insulating layer; a charge storage electrode connected to said pad polysilicon layer, whereby when a voltage is applied to said word line, said vertical channel region is formed so that a signal transmitter is transferred from said bit line to said charge storage electrode.
Claim 3
Dependent Claim
46 words
A dynamic random access memory according to claim 1, wherein said bit line junction region and said charge storage electrode junction region are formed in such a way that they overlap with the word line, and insulated from the word line via the gate oxide layer.
Claim 4
Dependent Claim
23 words
A dynamic random access memory according to claim 1, wherein said bit line is formed lengthwise at the bottom of the silicon substrate.
Claim 5
Dependent Claim
31 words
A dynamic random access memory according to claim 1, wherein said word line is formed lengthwise along a slot on the silicon substrate so that it vertically crosses the bit line.
Claim 6
Dependent Claim
42 words
A dynamic random access memory according to claim 1, wherein said channel is formed on said silicon substrate of the trench wall surface directed toward the word line from a region where the bit line and a word line cross each other.
Claim 7
Dependent Claim
19 words
A dynamic random access memory according to claim 1, wherein a switching transistor is formed in said silicon substrate.
Claim 8
Dependent Claim
51 words
A dynamic random access memory according to claim 1, wherein said signal transmitter is moved from the bit line to the channel region through a bit line junction region and then moves to the pad polysilicon layer through the charge storage electrode junction region, finally, it reaches the charge storage electrode.
Claim 9
Dependent Claim
25 words
A dynamic random access memory according to claim 1, wherein said charge storage electrode is formed on said pad polysilicon thereby forming a stacked capacitor.
Claim 10
Dependent Claim
35 words
A dynamic random access memory according to claim 8, wherein said stacked capacitor is formed on the surface of the substrate so as to maximize the area of the charge storage capacitor per unit cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |