Dynamic random access memory device

Claim 2

A dynamic random access memory (DRAM) device with extended memory storage time, said DRAM device comprising: a bit line for writing information to storage when a potential is applied thereto; means for storing charge; and a bipolar transistor for connecting said charge storing means to said bit line, said bipolar transistor being formed in a semiconductor having a bandgap greater than the bandgap of silicon and said transistor having a base region, an emitter region connected to said bit line, and a floating collector region: wherein said DRAM device is generation limited i.e., a charge is stored by creating a deficit of carriers in the floating collector region, the storage time being determined by the rate at which carriers are created again in the collector region by thermal generation.

Claim 3

A DRAM device according to claim 1 wherein said semiconductor comprises gallium arsenide.

Claim 4

A DRAM device according to claim 1 wherein said semiconductor comprises aluminum-gallium-arsenide.

Claim 5

A DRAM device according to claim 1 further comprising a word line connected to said transistor for addressing bit line data from said bit line, wherein said bit line data comprise a first voltage or a second voltage for respectively defining a logic one or logic zero.

Claim 6

A dynamic random access memory (DRAM) cell with extended memory storage time, which comprises: a bipolar transistor formed in a semiconductor having a bandgap greater than the bandgap of silicon, said transistor having a base region, an emitter region, and a floating collector region; a charge storage device formed in said semiconductor and electrically connected to said floating collector region of said bipolar transistor; a bit line connected to said emitter region of said bipolar transistor for writing data to and reading data from said DRAM cell; and a word line connected to said base region of said bipolar transistor for addressing bit line data from said bit line; wherein said DRAM cell is generation limited, i.e., a charge is stored by creating a deficit of carriers in the floating collector region, the storage time being determined by the rate at which carriers are created again in the collector region by thermal generation.

Claim 7

A dynamic random access memory (DRAM) cell with extended memory storage time, which comprises: a bipolar transistor formed in a semiconductor having a bandgap greater than the bandgap of silicon, said transistor having a base region, an emitter region, and a floating collector region; a charge storage device formed in said semiconductor and electrically connected to said floating collector region of said bipolar transistor; a bit line connected to said emitter region of said bipolar transistor for writing data to and reading data from said DRAM cell; and a word line connected to said base region of said bipolar transistor for addressing bit line data from said bit line; wherein said DRAM cell is generation limited, i.e., a charge is stored by creating a deficit of carriers in the floating collector region, the storage time being determined by the rate at which carriers are created again in the collector region by thermal generation.

Claim 8

A DRAM device according to claim 5 wherein said semiconductor comprises GaAs.

Claim 9

A DRAM device according to claim 5 wherein said semiconductor comprises AlGaAs.

Claim 10

A dynamic random access memory (DRAM) cell which comprises: a substrate defining a ground plate of a storage capacitor; a first region of semiconductor material having a bandgap greater than the bandgap of silicon and having a first conductivity type; a second region of semiconductor material having a bandgap greater than the bandgap of silicon and having an opposite conductivity type from said first region, said second region being disposed on said first region and defining a floating collector region of a bipolar transistor; a third region of semiconductor material having a bandgap greater than the bandgap of silicon and having the same conductivity type as said first region , said third region being disposed on said second region and defining a base region of said transistor; and a fourth region of semiconductor material having a bandgap greater than the bandgap of silicon and having the same conductivity type as said second region, said fourth region being disposed on said third region and defining an emitter region of said transistor; wherein said first, second and third regions form said storage capacity, and said second, third, and fourth regions form said bipolar access transistor; and wherein said DRAM cell is generation limited i.e., a charge is stored by creating a deficit of carriers in the floating collector region, the storage time being determined by the rate at which carriers are created again in the collector region by thermal generation.

Claim 11

A dynamic random access memory (DRAM) cell which comprises: a substrate defining a ground plate of a storage capacitor; a first region of semiconductor material having a bandgap greater than the bandgap of silicon and having a first conductivity type; a second region of semiconductor material having a bandgap greater than the bandgap of silicon and having an opposite conductivity type from said first region, said second region being disposed on said first region and defining a floating collector region of a bipolar transistor; a third region of semiconductor material having a bandgap greater than the bandgap of silicon and having the same conductivity type as said first region , said third region being disposed on said second region and defining a base region of said transistor; and a fourth region of semiconductor material having a bandgap greater than the bandgap of silicon and having the same conductivity type as said second region, said fourth region being disposed on said third region and defining an emitter region of said transistor; wherein said first, second and third regions form said storage capacity, and said second, third, and fourth regions form said bipolar access transistor; and wherein said DRAM cell is generation limited i.e., a charge is stored by creating a deficit of carriers in the floating collector region, the storage time being determined by the rate at which carriers are created again in the collector region by thermal generation.

Claim 12

A DRAM cell according to claim 8, further comprising ohmic contacts to said base region and said emitter region, respectively, for biasing said bipolar transistor.

Claim 13

A dynamic random access memory (DRAM) cell which comprises: a substrate defining a ground plate of a storage capacitor; a first region of semiconductor material having a bandgap greater than the bandgap of silicon and having a first conductivity type; a second region of semiconductor material having a bandgap greater than the bandgap of silicon and having an opposite conductivity type from said first region, said second region being disposed on said first region and defining a floating collector region of a bipolar transistor; a third region of semiconductor material having a bandgap greater than the bandgap of silicon and having the same conductivity type as said first region, said third region being disposed on said second region and defining a base region of said transistor; and a fourth region of semiconductor material having a bandgap greater than the bandgap of silicon and having the same conductivity type as said second region, said fourth region being disposed on said third region and defining an emitter region of said transistor; wherein said first, second and third regions form said storage capacitor, and said second, third and fourth regions form said bipolar access transistor; and wherein said bipolar transistor switches said cell between high and low voltage memory configurations, and whereby a forward bias applied from said base region to said floating collector region will encourage a flow of carriers from said floating collector region to said base region so that said storage capacitor will be charged and will retain stored charge when such bias is removed.

Claim 14

A dynamic random access memory (DRAM) cell which comprises: a substrate defining a ground plate of a storage capacitor; a first region of semiconductor material having a bandgap greater than the bandgap of silicon and having a first conductivity type; a second region of semiconductor material having a bandgap greater than the bandgap of silicon and having an opposite conductivity type from said first region, said second region being disposed on said first region and defining a floating collector region of a bipolar transistor; a third region of semiconductor material having a bandgap greater than the bandgap of silicon and having the same conductivity type as said first region, said third region being disposed on said second region and defining a base region of said transistor; and a fourth region of semiconductor material having a bandgap greater than the bandgap of silicon and having the same conductivity type as said second region, said fourth region being disposed on said third region and defining an emitter region of said transistor; wherein said first, second and third regions form said storage capacitor, and said second, third and fourth regions form said bipolar access transistor; and wherein said bipolar transistor switches said cell between high and low voltage memory configurations, and whereby a forward bias applied from said base region to said floating collector region will encourage a flow of carriers from said floating collector region to said base region so that said storage capacitor will be charged and will retain stored charge when such bias is removed.

Claim 15

A DRAM cell, according to claim 10, wherein said regions of semiconductor material comprise GaAs.

Claim 16

A DRAM cell, according to claim 10, wherein said regions of semiconductor material comprises AlGaAs.

Claim 17

A DRAM cell, according to claim 11, further comprising an undoped GaAs layer between said first region and said second region.

Claim 18

A DRAM cell, according to claim 10, wherein said first conductivity type comprises p-type GaAs and said second conductivity type comprises n-type GaAs.

Claim 19

A DRAM cell, according to claim 10, wherein said first conductivity type comprises n-type GaAs and said second conductivity type comprises p-type GaAs.

Claim 20

A DRAM cell, according to claim 12, further comprising an undoped GaAs layer between said second region and said third region.

Claim 21

A DRAM cell according to claim 8 further comprising: a bit line connected to said emitter region of said bipolar transistor for writing data to and reading data from said DRAM cell; and a word line connected to said base region of said bipolar transistor for addressing bit line data from said bit line; wherein said bit line data comprise a first voltage or a second voltage for respectively defining a logic one or logic zero.

Claim 24

A method of storing bit or word data in nonvolatile fashion in a RAM cell according to claim 18 wherein said wide-bandgap semiconductor comprises a semiconductor with a bandgap greater than the bandgap of silicon.