US3876992A
Expired / Lapsed
US
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Bipolar transistor memory with capacitive storage
Assignee: International Business Machines Corp
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Filing: 1974-05-06
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Granted: 1975-04-08
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Expires: 1994-05-06
Abstract
Abstract The memory is formed of an array of cells, each of which is coupled to the word and bit lines. Each cell comprises only a bipolar transistor coupled to a capacitor. The base terminal of the transistor is connected directly to the word line and either the emitter terminal or the collector terminal of the transistor may be coupled in series with the capacitor. In one embodiment the transistor, in series with the capacitor, is connected between a bit/sense line and a reference voltage and in another embodiment between the bit line and a sense line. Information is stored in the capacitor by discharing the capacitor through the transistor and information is read out by charging the capacitor. During a read/erase operation the word line, which is normally at a quiescent voltage, is raised to a higher voltage to render the transistor conductive between its collector and emitter. Simultaneously, the bit line has impressed upon it a positive voltage. During a write operation the word line has impressed upon it a voltage which is between its quiescent voltage and its read/erase voltage. If a 0 is to be stored, the bit line is maintained at a high level and the capacitor charged. If a 1 is to be stored, the voltage on the bit line is substantially reduced so that the capacitor is discharged. During the read operations a signal is transmitted to the bit line if a 1 has been stored previously.
Inventors
- 👤 Wilbur David Pricer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:55
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
255 words
A semiconductor storage system comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells, each of said memory cell being coupled to one of said word lines and one of said bit lines, each of said memory cells comprising only a transistor, having an emitter, a base and a collector, and a charge storage means, the emitter collector circuit of the transistor being coupled between the storage means and the bit line, the base of the transistor being coupled to the word line, and means for writing information into the reading information out of a selected memory cell comprising, means for selectively setting a reference voltage on a selected word line to render the transistor in the cell nonconductive, means for simultaneously setting on a selected bit line a quiescent voltage greater than the reference voltage applied to the word line, means for raising the voltage on the word line to a first voltage greater than the reference voltage and sufficient to render the transistor conductive and simultaneously lowering the voltage on the bit line below the quiescent voltage to write a first binary information state in the cell by discharging the storage means, and means for raising the voltage on the selected word line to a second voltage greater than the first voltage, while simultaneously maintaining the selected bit line at its quiescent voltage to read the charge state in the capacitor and to store charge in the capacitor to establish in the capacitor the second binary state.
Claim 2
Dependent Claim
255 words
A semiconductor storage system comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells, each of said memory cell being coupled to one of said word lines and one of said bit lines, each of said memory cells comprising only a transistor, having an emitter, a base and a collector, and a charge storage means, the emitter collector circuit of the transistor being coupled between the storage means and the bit line, the base of the transistor being coupled to the word line, and means for writing information into the reading information out of a selected memory cell comprising, means for selectively setting a reference voltage on a selected word line to render the transistor in the cell nonconductive, means for simultaneously setting on a selected bit line a quiescent voltage greater than the reference voltage applied to the word line, means for raising the voltage on the word line to a first voltage greater than the reference voltage and sufficient to render the transistor conductive and simultaneously lowering the voltage on the bit line below the quiescent voltage to write a first binary information state in the cell by discharging the storage means, and means for raising the voltage on the selected word line to a second voltage greater than the first voltage, while simultaneously maintaining the selected bit line at its quiescent voltage to read the charge state in the capacitor and to store charge in the capacitor to establish in the capacitor the second binary state.
Claim 3
Dependent Claim
260 words
A semiconductor storage system comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells, each of said memory cells being coupled to one of said word lines and one of said bit lines, each of said memory cells comprising only a transistor, having an emitter, a base and a collector, and a charge storage means, the emitter collector circuit of the transistor being coupled between the storage means and the bit line, the base of the transistor being coupled to the word line, and means for writing information into and reading information out of selected memory cells, and means comprising first bias voltage means for selectively setting on a selected word line a first one of two different bias voltages of the same polarity, second voltage bias for selective setting on a selected bit line a first one of two different bias voltages of the same polarity simultaneously with the application of the first bias voltage of the first voltage means to the selected word line to establish a uniform charge state in a selected charge storage means, and means for altering the voltage on the selected bit line to the other of said bias voltages, while simultaneously altering the bias voltage on the selected word line to the other of said bias voltages to read the charge state on the capacitor, said charge storage means comprising a capacitor having first and second terminals, one terminal of which is coupled to the emitter of said transistor and the other terminal is coupled to ground.
Claim 4
Dependent Claim
260 words
A semiconductor storage system comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells, each of said memory cells being coupled to one of said word lines and one of said bit lines, each of said memory cells comprising only a transistor, having an emitter, a base and a collector, and a charge storage means, the emitter collector circuit of the transistor being coupled between the storage means and the bit line, the base of the transistor being coupled to the word line, and means for writing information into and reading information out of selected memory cells, and means comprising first bias voltage means for selectively setting on a selected word line a first one of two different bias voltages of the same polarity, second voltage bias for selective setting on a selected bit line a first one of two different bias voltages of the same polarity simultaneously with the application of the first bias voltage of the first voltage means to the selected word line to establish a uniform charge state in a selected charge storage means, and means for altering the voltage on the selected bit line to the other of said bias voltages, while simultaneously altering the bias voltage on the selected word line to the other of said bias voltages to read the charge state on the capacitor, said charge storage means comprising a capacitor having first and second terminals, one terminal of which is coupled to the emitter of said transistor and the other terminal is coupled to ground.
Claim 5
Dependent Claim
38 words
The memory of claim 2 wherein said charge storage means is a capacitor having first and second terminals the first of said terminals being coupled to said collector and the second of said terminals being coupled to ground.
Claim 6
Dependent Claim
22 words
The memory of claim 2 wherein there is further provided a separate sense line coupled to said collector-emitter circuit of said transistor.
Claim 7
Dependent Claim
40 words
The memory system of claim 4 wherein said charge storage means is a capacitor having first and second terminals said first terminal being coupled to the emitter of said transistor and said second terminal being coupled to said sense line.
Claim 8
Dependent Claim
40 words
The memory system of claim 4 wherein said charge storage means is a capacitor having first and second terminals, said first terminal being coupled to said collector of said transistor and said second terminal being coupled to said sense line.
Claim 9
Dependent Claim
68 words
A memory system having intersecting word lines and bit lines and semiconductor memory cells coupling said word and said bit lines, each memory cell comprising, a terminal, a capacitor, and a transistor having a base directly connected to one of said word lines and an emitter-collector circuit, said circuit forming a series circuit with said capacitor, said series circuit being coupled between said bit line and said terminal.
Claim 10
Dependent Claim
68 words
A memory system having intersecting word lines and bit lines and semiconductor memory cells coupling said word and said bit lines, each memory cell comprising, a terminal, a capacitor, and a transistor having a base directly connected to one of said word lines and an emitter-collector circuit, said circuit forming a series circuit with said capacitor, said series circuit being coupled between said bit line and said terminal.
Claim 11
Dependent Claim
15 words
The memory system of claim 7 wherein said terminal is a point of reference potential.
Claim 12
Dependent Claim
11 words
The memory system of claim 7 wherein said terminal is ground.
Claim 13
Dependent Claim
29 words
The memory system of claim 7 wherein there is further provided means, including multilevel pulses of one polarity for writing information into and reading information out of said capacitor.
Claim 14
Dependent Claim
24 words
The memory system of claim 7 wherein said system further includes sense lines and said terminal is formed on one of said sense lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-07 | 1978-10-07 | 1979-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-07 | 1982-10-07 | 1983-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-07 | 1986-10-07 | 1987-04-08 | $7700.00 | Window Closed / Lapsed |