US3715732A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-terminal npn-pnp transistor memory cell
Assignee: AT&T Inc
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Filing: 1971-12-09
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Granted: 1973-02-06
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Expires: 1991-12-09
Abstract
Abstract A semiconductor memory array contains memory cells each of which contains an NPN transistor and a PNP transistor. The collector and base of the NPN transistor are respectively coupled to the base and collector of the PNP transistor. Bit information is written into the cell by causing or inhibiting conduction in the PNP transistor in order to set the potential of the base of the NPN transistor to one of two values which represent, respectively, a ''''1'''' and a ''''0.'''' A positive polarity voltage pulse applied to the collector of the NPN transistor causes information previously stored in the cell to be read out.
Inventors
- 👤 D Lynes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/41; G11C11/411
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
143 words
Semiconductor memory apparatus comprising: a plurality of interconnected memory cells, each of which comprises two terminals and is adapted to store bit information; each of said memory cells comprising first and second junction transistors which are complementary; the first and second terminals being respectively connected to the collector of the first transistor and the emitter of the second transistor; the collector and base of each of the first transistors being coupled to the base and collector, respectively, of each of the second transistors; the base of each of said first transistors being coupled to the first terminal of each cell via a first capacitance and being coupled to the second terminal of each cell via a second capacitance; the first transistor is an NPN type transistor; the second transistor is a PNP type transistor; and the emitters of both transistors are electrically coupled.
Claim 2
Dependent Claim
143 words
Semiconductor memory apparatus comprising: a plurality of interconnected memory cells, each of which comprises two terminals and is adapted to store bit information; each of said memory cells comprising first and second junction transistors which are complementary; the first and second terminals being respectively connected to the collector of the first transistor and the emitter of the second transistor; the collector and base of each of the first transistors being coupled to the base and collector, respectively, of each of the second transistors; the base of each of said first transistors being coupled to the first terminal of each cell via a first capacitance and being coupled to the second terminal of each cell via a second capacitance; the first transistor is an NPN type transistor; the second transistor is a PNP type transistor; and the emitters of both transistors are electrically coupled.
Claim 3
Dependent Claim
143 words
Semiconductor memory apparatus comprising: a plurality of interconnected memory cells, each of which comprises two terminals and is adapted to store bit information; each of said memory cells comprising first and second junction transistors which are complementary; the first and second terminals being respectively connected to the collector of the first transistor and the emitter of the second transistor; the collector and base of each of the first transistors being coupled to the base and collector, respectively, of each of the second transistors; the base of each of said first transistors being coupled to the first terminal of each cell via a first capacitance and being coupled to the second terminal of each cell via a second capacitance; the first transistor is an NPN type transistor; the second transistor is a PNP type transistor; and the emitters of both transistors are electrically coupled.
Claim 4
Dependent Claim
143 words
Semiconductor memory apparatus comprising: a plurality of interconnected memory cells, each of which comprises two terminals and is adapted to store bit information; each of said memory cells comprising first and second junction transistors which are complementary; the first and second terminals being respectively connected to the collector of the first transistor and the emitter of the second transistor; the collector and base of each of the first transistors being coupled to the base and collector, respectively, of each of the second transistors; the base of each of said first transistors being coupled to the first terminal of each cell via a first capacitance and being coupled to the second terminal of each cell via a second capacitance; the first transistor is an NPN type transistor; the second transistor is a PNP type transistor; and the emitters of both transistors are electrically coupled.
Claim 5
Dependent Claim
33 words
The apparatus of claim 1 further comprising: first voltage control circuits coupled to the first terminals; second voltage control circuits coupled to the second terminals; and conduction detectors coupled to the second terminals.
Claim 6
Dependent Claim
251 words
Semiconductor memory apparatus comprising: a plurality of interconnected memory cells, each of which comprises first and second terminals and is adapted to store bit information; each of the memory cells comprising first and second junction transistors which are complementary; the collector and base of each of the first transistors being coupled to the base and collector, respectively, of each of the second transistors; the collector of the first transistor and the emitter of the second transistor being the first and second terminals, respectively; the base of each of the first transistors being coupled to the first terminal via a first capacitance and being coupled to the second terminal via a second capacitance; first write-in means coupled to the terminals of the cells for selectively forward biasing the emitter-base junction of the second transistor of a selected cell such that the potential of the base of the first transistor of the selected cell is set to a first potential; second write-in means coupled to the terminals of the cells for causing the potential of the base of the first transistor of a selected memory cell to be set to a second potential; read-out means coupled to each of said first terminals of each of the cells for causing conduction in the first transistor of a selected cell only if the potential of the base of the first transistor is set to the first potential; and detection means coupled to the cells for detecting conduction in the first transistors of each memory cell.
Claim 7
Dependent Claim
251 words
Semiconductor memory apparatus comprising: a plurality of interconnected memory cells, each of which comprises first and second terminals and is adapted to store bit information; each of the memory cells comprising first and second junction transistors which are complementary; the collector and base of each of the first transistors being coupled to the base and collector, respectively, of each of the second transistors; the collector of the first transistor and the emitter of the second transistor being the first and second terminals, respectively; the base of each of the first transistors being coupled to the first terminal via a first capacitance and being coupled to the second terminal via a second capacitance; first write-in means coupled to the terminals of the cells for selectively forward biasing the emitter-base junction of the second transistor of a selected cell such that the potential of the base of the first transistor of the selected cell is set to a first potential; second write-in means coupled to the terminals of the cells for causing the potential of the base of the first transistor of a selected memory cell to be set to a second potential; read-out means coupled to each of said first terminals of each of the cells for causing conduction in the first transistor of a selected cell only if the potential of the base of the first transistor is set to the first potential; and detection means coupled to the cells for detecting conduction in the first transistors of each memory cell.
Claim 8
Dependent Claim
32 words
The apparatus of claim 3 wherein: the first transistor is an NPN type transistor and the second transistor is a PNP type transistor; and the emitters of both transistors are electrically coupled.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-06 | 1976-08-07 | 1977-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-06 | 1980-08-07 | 1981-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-06 | 1984-08-07 | 1985-02-06 | $7700.00 | Window Closed / Lapsed |