Information storage device

Claim 2

An information storage device comprising: a first voltage source representing a binary one value of information; a second voltage source representing a binary zero value of information, said second source different than said first source; a first switch member normally biased in an open position and switchable between either one of said two voltage sources; a second switch member normally biased in an open position and switchable to a closed position, said second switch member electrically connected to said first switch member; impedance means electrically connected between the closed position of said second switch member and ground; and a capacitor electrically connected between said first and second switch members and ground, said capacitor charged through said first switch member to either one of said two voltage sources in accordance with the information to be stored and said capacitor discharged through said second switch member and said impedance means developing an electrical signal across said impedance means representative of the value of the stored information.

Claim 3

A information storage device for storing binary valued information comprising: a first field-effect transistor having an input electrode, an output electrode and a control electrode, a second field-effect transistor having an input electrode, an output electrode and a control electrode, said control electrode electrically connected to the output electrode of said first transistor, information supply means supplying a first potential for binary one information and a second potential for binary zero information, said supply means electrically connected to the input electrode of said first transistor, control means electrically connected to the control electrode of said first transistor controlling the conduction of said first transistor. supply means electrically connected to the input electrode of said second transistor supplying a source of potential to be conducted through said second transistor in response to the control electrode of said second transistor, impedance means electrically connected to the output electrode of said second transistor, and a capacitor electrically connected between the control electrode of said second transistor and ground, said capacitor charged to the potential of said information supply means through said first transistor and electrically controlling the conduction of said second transistor in response to said supply means.

Claim 4

A information storage device for storing binary valued information comprising: a first field-effect transistor having an input electrode, an output electrode and a control electrode, a second field-effect transistor having an input electrode, an output electrode and a control electrode, said control electrode electrically connected to the output electrode of said first transistor, information supply means supplying a first potential for binary one information and a second potential for binary zero information, said supply means electrically connected to the input electrode of said first transistor, control means electrically connected to the control electrode of said first transistor controlling the conduction of said first transistor. supply means electrically connected to the input electrode of said second transistor supplying a source of potential to be conducted through said second transistor in response to the control electrode of said second transistor, impedance means electrically connected to the output electrode of said second transistor, and a capacitor electrically connected between the control electrode of said second transistor and ground, said capacitor charged to the potential of said information supply means through said first transistor and electrically controlling the conduction of said second transistor in response to said supply means.

Claim 5

The information storage device according to claim 2 wherein said first and second field-effect transistors are P-enhancement-mode Insulated gate field-effect transistors.

Claim 6

The information storage device according to claim 2 further including regenerating means electrically coupled between the output electrode of said second transistor and the input electrode of said first transistor to maintain the charge potential on said capacitor.

Claim 7

A memory system comprising: a plurality of memory cell storage means arranged to represent a unit of information having a codal representation equal to number of cells, an information supply means supplying the codal representation of a unit of information, an input control conductor electrically connecting all of said plurality of memory cell storage means with said information supply means, an input supply conductor electrically connecting each cell storage means with said information supply means, output means, an output control conductor electrically connecting all of said plurality of memory cell storage means with said output means, an output sense conductor electrically connecting each cell storage means with said output means, and regeneration means electrically coupled between said output sense conductor and said input supply conductor, said regenerating means operatively responsive to the said output control conductor to transfer the electrical signal generated by said cell storage means on said output sense conductor to said input supply conductor to retain said information within said memory cell storage means.

Claim 8

A memory system comprising: a plurality of memory cell storage means arranged to represent a unit of information having a codal representation equal to number of cells, an information supply means supplying the codal representation of a unit of information, an input control conductor electrically connecting all of said plurality of memory cell storage means with said information supply means, an input supply conductor electrically connecting each cell storage means with said information supply means, output means, an output control conductor electrically connecting all of said plurality of memory cell storage means with said output means, an output sense conductor electrically connecting each cell storage means with said output means, and regeneration means electrically coupled between said output sense conductor and said input supply conductor, said regenerating means operatively responsive to the said output control conductor to transfer the electrical signal generated by said cell storage means on said output sense conductor to said input supply conductor to retain said information within said memory cell storage means.