Two-terminal nondestructive read jfet-npn transistor semiconductor memory

Claim 1

A semiconductor memory apparatus comprising: a plurality of interconnected memory cells, each of which comprises two terminals and is adapted to store bit information; each of the memory cells comprising a JFET and a junction transistor, the gate and drain of the JFET being coupled to the collector and base of the junction transistor, respEctively; the source and emitter of each cell serving as the first and second terminal, respectively; a capacitor coupled to the common node of the collector and gate of each memory cell; first write-in means coupled to the cells for causing conduction in the JFET and junction transistor of a selected cell in order to set the potential of the gate collector node of the selected cell set to a first level which is defined as a ''''0''''; second write-in means coupled to the cells for selectively causing the source gate junction of a selected memory cell to be forward-biased while the emitter base junction of the junction transistor of selected cell is reverse-biased in order to set the potential of the corresponding gate collector node to a second level which is defined as a ''''1'''' ; and readout means coupled to the cells for first increasing and then decreasing the potential of the source of a selected memory cell to cause bit information stored in the selected cell to be nondestructively read out.

Claim 6

A method for performing a memory function utilizing at least one memory cell which comprises a JFET, the gate and drain of which are coupled to the collector and base of a junction transistor, respectively, consisting of the steps of: writing a ''''1'''' into the memory cell by forward-biasing the source gate junction of the JFET while inhibiting current flow through the junction transistor in order to set the potential of the gate to a level defined as a ''''1'''' level; writing a '''' 0'''' into the memory cell by forward biasing the source gate junction of the JFET and causing the JFET and the junction transistor to conduct such that the potential of the gate of the JFET is set to a level defined as a ''''0'''' level; and reading out bit information stored within the memory cell by first increasing and then decreasing the potential of the source such that conduction occurs in the JFET and the NPN transistor if the cell stores a ''''0''''.

Claim 7

A method for performing a memory function utilizing at least one memory cell which comprises a JFET, the gate and drain of which are coupled to the collector and base of a junction transistor, respectively, consisting of the steps of: writing a ''''1'''' into the memory cell by forward-biasing the source gate junction of the JFET while inhibiting current flow through the junction transistor in order to set the potential of the gate to a level defined as a ''''1'''' level; writing a '''' 0'''' into the memory cell by forward biasing the source gate junction of the JFET and causing the JFET and the junction transistor to conduct such that the potential of the gate of the JFET is set to a level defined as a ''''0'''' level; and reading out bit information stored within the memory cell by first increasing and then decreasing the potential of the source such that conduction occurs in the JFET and the NPN transistor if the cell stores a ''''0''''.