Nondestructive memory array

Claim 1

A MEMORY CELL COMPRISING FIRST AND SECOND TRANSISTORS OF SAME CONDUCTIVITY TYPE AND EACH TRANSISTOR HAVING AN EMITTER AND COLLECTOR AND A BASE CIRCUIT, A BISTABLE STORAGE ELEMENT HAVING FIRST AND SECOND STORAGE STATES AND FIRST AND SECOND INPUT TERMINALS CONNECTED IN SAID BASE CIRCUITS OF SAID FIRST AND SECOND TRANSISTORS, RESPECTIVELY, FIRST MEANS CONNECTED TO SAID COLLECTOR OF SAID FIRST TRANSISTOR, SECOND MEANS CONNECTED TO SAID COLLECTOR OF SAID SECOND TRANSISTOR, THIRD MEANS CONNECTED TO SAID EMITTERS OF SAID FIRST AND SAID SECOND TRANSISTORS, SAID FIRST AND SAID SECOND TRANSISTORS BEING BIASED FOR NORMAL TRANSISTOR OPERATION WHEN SAID THIRD MEANS IS SINGULARLY ENERGIZED, SAID FIRST AND SAID SECOND TRANSISTORS BEING BIASED FOR SATURATED OPERATION WHEN SAID FIRST AND SAID SECOND MEANS, RESPECTIVELY, AND SAID THIRD MEANS ARE CONCURRENTLY ENERGIZED, SAID BASE CIRCUITS OF SAID FIRST AND SAID SECOND TRANSISTORS SUPPORTING CONDUCTION IN SAID FIRST AND SAID SECOND TRANSISTORS, RESPECTIVELY, WHILE SAID STORAGE ELEMENT IS IN SAID FIRST AND SAID SECOND STATES, RESPECTIVELY, SAID STORAGE ELEMENT BEING RESPONSIVE TO SAID FIRST AND SAID SECOND TRANSISTORS WHEN SATURATED TO SWITCH BETWEEN SAID FIRST AND SAID SECOND STORAGE STATES, RESPECTIVELY, AND SENSING MEANS CONNECTED TO SAID COLLECTORS OF SAID FIRST AND SAID SECOND TRANSISTORS, RESPECTIVELY, FOR ASCERTAINING THE STORAGE STATE OF SAID STORAGE ELEMENT, SAID FIRST AND SAID SECOND STORAGE STATES BEING INDICATED BY NORMAL TRANSISTOR OPERATION IN SAID FIRST AND SAID SECOND TRANSISTORS, RESPECTIVELY, WHEN SAID THIRD MEANS IS SINGULARLY ENERGIZED.