US4807008A
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Static memory cell using a heterostructure complementary transistor switch
Assignee: Conexant Systems LLC
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Filing: 1987-09-14
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Granted: 1989-02-21
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Expires: 2007-09-14
Abstract
Abstract A heterostructure complementary transistor switch (HCTS) is fabricated using epitaxial layers on a substrate to form the desired P-N-P-N (or N-P-N-P) complementary structure in III-V compound semiconductor materials. Two HCTS are formed on a single substrate to form a memory cell. A collector and a base on one of the HCTs are connected to a base and a collector, respectively, on the other HCTS to form the memory cell.
Inventors
- 👤 Mau-Chung F. Chang
- 👤 Peter M. Asbeck
- 👤 Keh-Chung Wang
- 👤 David L. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; H; H10; H10B; H10B10/00; H10B10/10; H10D; H10D10/00; H10D10/80; H10D10/821; H10D10/891; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10D86/00; H10D86/01
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
165 words
A heterostructure complementary transistor switch (HCTS) comprising: a semi-insulating substrate; a first semiconducting layer of a one-type conductivity on the substrate; an emitter contact on the first semiconducting layer of one-type conductivity forming an emitter of a first heterojunction bipolar transistor (HBT); a second semiconducting layer of opposite-type conductivity on the first semiconducting layer forming a heterojunction between the first and second layers; a contact on the second semiconducting layer forming the base of the first HBT and a collector of a second HBT; a third semiconducting layer of the one-type conductivity on the second semiconducting layer forming a heterojunction between the second and third layers; a contact on the third semiconducting layer forming a collector of the first HBT and a base of the second HBT; a fourth semiconducting layer of the opposite-type conductivity on the third semiconducting layer forming a heterojunction between the third and fourth layers; and an emitter contact on the fourth semiconducting layer forming an emitter of the second HBT.
Claim 2
Dependent Claim
165 words
A heterostructure complementary transistor switch (HCTS) comprising: a semi-insulating substrate; a first semiconducting layer of a one-type conductivity on the substrate; an emitter contact on the first semiconducting layer of one-type conductivity forming an emitter of a first heterojunction bipolar transistor (HBT); a second semiconducting layer of opposite-type conductivity on the first semiconducting layer forming a heterojunction between the first and second layers; a contact on the second semiconducting layer forming the base of the first HBT and a collector of a second HBT; a third semiconducting layer of the one-type conductivity on the second semiconducting layer forming a heterojunction between the second and third layers; a contact on the third semiconducting layer forming a collector of the first HBT and a base of the second HBT; a fourth semiconducting layer of the opposite-type conductivity on the third semiconducting layer forming a heterojunction between the third and fourth layers; and an emitter contact on the fourth semiconducting layer forming an emitter of the second HBT.
Claim 3
Dependent Claim
21 words
The HCTS as claimed in claim 1 wherein the one-type conductivity is n-type conductivity and the opposite-type conductivity is p-type conductivity.
Claim 4
Dependent Claim
22 words
The HCTS as claimed in claim 1 wherein the one-type conductivity is p-type conductivity and the opposite type conductivity is n-type conductivity.
Claim 5
Dependent Claim
71 words
The HCTS as claimed in claim 1 including: a first Schottky metal deposit on the third layer forming a Schottky diode to the base of the second HBT; a second Schottky metal deposit on the third layer; an ohmic contact on the second layer; and a conductor joining the ohmic contact to the second Schottky metal deposit, thereby providing a Schottky diode between the bases of the first and second HBTs.
Claim 6
Dependent Claim
98 words
A memory cell using a heterostructure complementary transistor switch (HCTS), comprising: a first HCTS as claimed in claim 1; a second HCTS as claimed in claim 1 having the same substrate and first semiconducting layer as the first HCTS, but being electrically isolated from the first HCTS; a first conductor connecting the collector of the first HBT on the first HCTS to the base of the first HBT on the second HCTS; and a second conductor connecting the base of the first HBT on the first HCTS to the collector of the first HBT on the second HCTS.
Claim 7
Dependent Claim
79 words
The memory cell as claimed in claim 5 wherein the first and second HCTS each include: a first Schottky metal deposit on the third layer forming a Schottky diode to the base of the second HBT; a second Schottky metal deposit on the third layer; an ohmic contact on the second layer; and a conductor joining the ohmic contact to the second Schottky metal deposit, thereby providing a Schottky diode between the bases of the first and second HBTs.
Claim 8
Dependent Claim
233 words
A heterostructure complementary transistor switch (HCTS) comprising: a semi-insulating substrate; a first semi conducting layer on the substrate comprising an n + -type GaAs sublayer, an n + -type InAs sublayer, and an n - -type GaAs layer; an emitter contact on the n + -type InAs sublayer of the first semiconducting layer forming an emitter of a first heterojunction bipolar transistor (HBT); a second semiconducting layer of p + -type InGaAs on the first semiconducting layer forming a heterojunction between the first and second layers; a contact on the second semiconducting layer forming the base of the first HBT and collector of a second HBT; a third semiconducting layer on the second semiconducting layer forming a heterojunction between the second and third layers, the third semiconducting layer comprising an n - -type GaAs sublayer and n + -type InGaAs sublayer; a contact on the n + -type InGaAs sublayer of the third semiconducting layer forming a collector of the first HBT and a base of the second HBT; a fourth semiconducting layer on the third semiconducting layer forming a heterojunction between the third and fourth layers, the fourth semiconducting layer comprising a p - -type AlGaAs sublayer, a p + -type GaAs sublayer, and a p + -type InSb sublayer; and an emitter contact on the p + -type InSb of the fourth semiconducting layer forming an emitter of the second HBT.
Claim 9
Dependent Claim
233 words
A heterostructure complementary transistor switch (HCTS) comprising: a semi-insulating substrate; a first semi conducting layer on the substrate comprising an n + -type GaAs sublayer, an n + -type InAs sublayer, and an n - -type GaAs layer; an emitter contact on the n + -type InAs sublayer of the first semiconducting layer forming an emitter of a first heterojunction bipolar transistor (HBT); a second semiconducting layer of p + -type InGaAs on the first semiconducting layer forming a heterojunction between the first and second layers; a contact on the second semiconducting layer forming the base of the first HBT and collector of a second HBT; a third semiconducting layer on the second semiconducting layer forming a heterojunction between the second and third layers, the third semiconducting layer comprising an n - -type GaAs sublayer and n + -type InGaAs sublayer; a contact on the n + -type InGaAs sublayer of the third semiconducting layer forming a collector of the first HBT and a base of the second HBT; a fourth semiconducting layer on the third semiconducting layer forming a heterojunction between the third and fourth layers, the fourth semiconducting layer comprising a p - -type AlGaAs sublayer, a p + -type GaAs sublayer, and a p + -type InSb sublayer; and an emitter contact on the p + -type InSb of the fourth semiconducting layer forming an emitter of the second HBT.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |