High performance thin film transistor (TFT) by solid phase epitaxial regrowth

Claim 2

A process for forming an active load in an integrated circuit fabricated on a single crystalline substrate, said process comprising: (a) forming a first dielectric layer superjacent existing surface of said single crystalline substrate; (b) planarizing said first dielectric layer; (c) forming a first semiconductive layer superjacent said planarized first dielectric layer; (d) patterning and etching said first semiconductive layer thereby forming a gate terminal to an active device; (e) forming dielectric spacers adjacent said patterned edges of said first semiconductive layer; (f) forming a second dielectric layer superjacent and coextensive to wafer surface resulting from step "e"; (g) patterning and etching a buried contact location thereby exposing portions of said single crystalline substrate; (h) forming a second semiconductive layer superjacent existing wafer surface resulting from step "g", said second semiconductive layer thereby making physical contact to said exposed portions of single crystalline substrate; (i) patterning and etching said second semiconductive material thereby forming a channel region for said active device and (j) growing a crystalline structure throughout said patterned second semiconductive material by using said single crystalline substrate as a seed source, said active device serving as said active load.

Claim 3

The process of claim 1, wherein said forming of said first semiconductive layer is by deposition and doping of polysilicon.

Claim 4

The process of claim 1, wherein said forming of said second dielectric layer is by low pressure chemical vapor deposition of oxide.

Claim 5

The process of claim 1, wherein said forming of said second dielectric layer is by low pressure chemical vapor deposition of a combination of oxide and nitride.

Claim 6

The process of claim 1, wherein said forming of said second semiconductive layer is by deposition and doping of amorphous polysilicon.

Claim 7

The process of claim 5, wherein said doping of said second semiconductive layer is by in-situ doping.

Claim 8

The process of claim 5, wherein said doping of said second semiconductive layer is by ion implantation.

Claim 9

The process of claim 1, wherein said forming of said crystalline material is by epitaxial regrowth of amorphous silicon throughout said second semiconductive layer by annealing, wherein said single crystalline substrate seed source is a silicon seed source and said second semiconductive layer is amorphous silicon.

Claim 10

The process of claim 8, wherein said annealing step comprises heating existing material on said substrate at a temperature range between 500° to 700° C. for approximately 15 minutes to 6 hours.

Claim 11

A process for forming a p-channel thin film transistor in an integrated circuit fabricated on a single crystalline silicon substrate, said process comprising: (a) depositing a first oxide layer superjacent existing surface of said single crystalline silicon substrate; (b) planarizing said first oxide layer; (c) depositing a first polysilicon layer superjacent said planarized first oxide layer; (d) patterning and etching said first polysilicon layer thereby forming a gate terminal to said thin film transistor; (e) depositing and etching oxide spacers adjacent said patterned edges of said first polysilicon layer; (f) forming a second dielectric layer superjacent and coextensive existing substrate surface resulting from step "e"; (g) patterning and etching a buried contact location thereby exposing portions of said single crystalline silicon substrate; (h) depositing a layer of amorphous silicon superjacent existing substrate surface resulting from step "g", said amorphous silicon layer thereby making physical contact to said exposed portions of single crystalline silicon substrate; (i) patterning and etching said amorphous silicon layer thereby forming a channel region for said thin film transistor; and (j) growing epitaxial silicon throughout said patterned amorphous silicon by using said single crystalline silicon substrate as a seed source by annealing existing material on said substrate at a temperature range between 500° to 700° C. for approximately 15 minutes to 6 hours.

Claim 12

A process for forming a p-channel thin film transistor in an integrated circuit fabricated on a single crystalline silicon substrate, said process comprising: (a) depositing a first oxide layer superjacent existing surface of said single crystalline silicon substrate; (b) planarizing said first oxide layer; (c) depositing a first polysilicon layer superjacent said planarized first oxide layer; (d) patterning and etching said first polysilicon layer thereby forming a gate terminal to said thin film transistor; (e) depositing and etching oxide spacers adjacent said patterned edges of said first polysilicon layer; (f) forming a second dielectric layer superjacent and coextensive existing substrate surface resulting from step "e"; (g) patterning and etching a buried contact location thereby exposing portions of said single crystalline silicon substrate; (h) depositing a layer of amorphous silicon superjacent existing substrate surface resulting from step "g", said amorphous silicon layer thereby making physical contact to said exposed portions of single crystalline silicon substrate; (i) patterning and etching said amorphous silicon layer thereby forming a channel region for said thin film transistor; and (j) growing epitaxial silicon throughout said patterned amorphous silicon by using said single crystalline silicon substrate as a seed source by annealing existing material on said substrate at a temperature range between 500° to 700° C. for approximately 15 minutes to 6 hours.