US5122476A
Expired / Lapsed
US
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Double DRAM cell
Assignee: Micron Technology Inc
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Filing: 1991-05-20
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Granted: 1992-06-16
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Expires: 2011-05-20
Abstract
Abstract A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.
Inventors
- 👤 Pierre C. Fazan
- 👤 Hiang C. Chan
- 👤 Yauh-Ching Liu
- 👤 Gurtej S. Sandhu
- 👤 Howard E. Rhodes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:15
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/37
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
307 words
A process for forming a double DRAM cell comprising: forming a first transistor (T1) on an active area of a silicon substrate by doping the active area with a source and a drain, forming a gate oxide over the active area and then forming an isolated word line (WL1) over the active area; forming a first storage capacitor (C1) to the transistor (T1); depositing an insulating layer on the first transistor (T1) to form a first cell including the first access transistor (T1) and the storage capacitor C1; opening a seed contact through the insulating layer to the drain, or source of the first transistor (T1); forming an intermediate substrate of monocrystalline silicon by selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) from the seed contact by: a. depositing a thick sacrificial layer over the insulating oxide layer; b. planarizing the sacrificial layer to form a planarized sacrificial block; c. depositing an oxide layer over the sacrificial block and forming an opening to the sacrificial block; d. etching away the sacrificial block utilizing the opening to form a cavity; and e. epitaxially growing a monocrystalline silicon within the cavity to form the intermediate substrate, forming a second transistor (T2) on the intermediate substrate by doping the intermediate substrate to form an active area, forming a source and a drain, forming a gate oxide over the active area and then forming an isolated word line (WL2) over the active area of the intermediate substrate; forming an insulated bit line to the drain of the second transistor (T2) as a common contact between the first (T1) and second (T2) transistor which are connected by the location of the seed contact; and forming a second storage capacitor (C2) for the second transistor (T2) to form a second cell including the second access transistor (T2) and second storage capacitor (C2).
Claim 2
Dependent Claim
307 words
A process for forming a double DRAM cell comprising: forming a first transistor (T1) on an active area of a silicon substrate by doping the active area with a source and a drain, forming a gate oxide over the active area and then forming an isolated word line (WL1) over the active area; forming a first storage capacitor (C1) to the transistor (T1); depositing an insulating layer on the first transistor (T1) to form a first cell including the first access transistor (T1) and the storage capacitor C1; opening a seed contact through the insulating layer to the drain, or source of the first transistor (T1); forming an intermediate substrate of monocrystalline silicon by selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) from the seed contact by: a. depositing a thick sacrificial layer over the insulating oxide layer; b. planarizing the sacrificial layer to form a planarized sacrificial block; c. depositing an oxide layer over the sacrificial block and forming an opening to the sacrificial block; d. etching away the sacrificial block utilizing the opening to form a cavity; and e. epitaxially growing a monocrystalline silicon within the cavity to form the intermediate substrate, forming a second transistor (T2) on the intermediate substrate by doping the intermediate substrate to form an active area, forming a source and a drain, forming a gate oxide over the active area and then forming an isolated word line (WL2) over the active area of the intermediate substrate; forming an insulated bit line to the drain of the second transistor (T2) as a common contact between the first (T1) and second (T2) transistor which are connected by the location of the seed contact; and forming a second storage capacitor (C2) for the second transistor (T2) to form a second cell including the second access transistor (T2) and second storage capacitor (C2).
Claim 3
Dependent Claim
35 words
The process as recited in claim 1 and wherein: the first storage capacitor (C1) is formed in a trench in the substrate and the second storage capacitor (C2) is stacked upon the second transistor (T2).
Claim 4
Dependent Claim
105 words
The process as recited in claim 2 and wherein the first storage capacitor (C1) is formed by the steps of: growing a first oxide layer on the substrate; depositing a first nitride layer over the oxide layer; forming a trench in the substrate; depositing an insulator material within the trench, the insulator material selected from the group consisting of an oxide, a nitride, an oxidized nitride, and a composite oxide/nitride layer; filling the trench with a polysilicon layer; planarizing the polysilicon layer; depositing a second oxide layer above the polysilicon and nitride layers; and then etching away sections of the first oxide and nitride layers.
Claim 5
Dependent Claim
141 words
The process as recited in claim 3 and wherein the first transistor (T1) is formed by the steps of: growing field oxide areas above the substrate in the etched sections; removing the first oxide and nitride layers in an active substrate area between the field oxide areas; growing a thin gate oxide in the active areas; depositing a polysilicon layer over the gate oxide; depositing a third oxide layer; etching the third oxide layer to form a gate electrode and a first word line; doping the active areas on either side of the gate area to form a source and a drain; depositing an oxide spacer adjacent opposite sides of the gate area; epitaxially growing a first connecting strap between the first storage capacitor and the first transistor source; and then epitaxially growing a second strap over the first transistor drain.
Claim 6
Dependent Claim
76 words
The process as recited in claim 1 and wherein the second transistor (T2) is formed by the steps of: doping the intermediate substrate to form a second source and a second drain; growing a gate oxide; depositing a gate polysilicon layer; etching the gate oxide and polysilicon layer; forming a pair of oxide spacers adjacent the gate; and then depositing a protective oxide layer over first and second transistors (T1, T2) and the first capacitor (C1).
Claim 7
Dependent Claim
92 words
The process as recited in claim 2 and wherein the second storage capacitor (C2) is formed by the steps of: depositing of an oxide layer over the bit line; opening a contact to a source of the second transistor (T2) by a masking and etching step; depositing a polysilicon layer; doping the polysilicon layer; etching the polysilicon layer to form a second capacitor bottom plate; depositing a capacitor cell dielectric material over the bottom plate; depositing a top capacitor cell plate over the dielectric; and then doping the top capacitor cell plate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-16 | 1995-12-16 | 1996-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-16 | 1999-12-16 | 2000-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-16 | 2003-12-16 | 2004-06-16 | $7700.00 | Window Closed / Lapsed |