Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor

Claim 1

A method for fabricating a memory cell for a semiconductor memory array comprising the steps of: Step (1) disposed an epitaxial layer on a semiconductor substrate and reactive ion etch a trench into the said epitaxial layer and substrate, Step (2) form a composite oxide/nitride/oxide storage insulator layer on the walls inside said trench, Step (3) fill said trench with polysilicon and planarize, Step (4) form a retrograde n-well in said epitaxial layer by a surface impurity implant and a deep impurity implant, Step (5) grow gate oxide and deposit polysilicon gate material for a PMOS type device and deposit an oxide film insulator layer over the PMOS gate and lithographically pattern said oxide film layer, Step (6) implant dopants into said n-well to provide graded source/drain junctions for PMOS and NMOS transistor devices, respectively, Step (7) open the surfaces of said source/drain regions for silicide formation wherein said gate element is protected from said silicide by said oxide film insulator layer formed in step (5), Step (8) form a lightly doped silicon film over said silicide, gate oxide and isolation regions wherein said lightly doped silicon film is deposited in polycrystalline structure and recrystallized by beam annealing, Step (9) define the NMOS type transistor device active area and grow thin NMOS gate oxide, Step (10) adjust channel threshold voltages by an impurity implant, Step (11) deposit polysilicon NMOS type transistor device gate material and pattern, Step (12) form oxide spacer regions on said NMOS gate electrode edges, Step (13) implant dopants to obtain source/drain junctions for a transfer device and grow oxide to cover the device.

Claim 2

A method for fabricating a memory cell for a semiconductor memory array comprising the steps of: Step (1) disposed an epitaxial layer on a semiconductor substrate and reactive ion etch a trench into the said epitaxial layer and substrate, Step (2) form a composite oxide/nitride/oxide storage insulator layer on the walls inside said trench, Step (3) fill said trench with polysilicon and planarize, Step (4) form a retrograde n-well in said epitaxial layer by a surface impurity implant and a deep impurity implant, Step (5) grow gate oxide and deposit polysilicon gate material for a PMOS type device and deposit an oxide film insulator layer over the PMOS gate and lithographically pattern said oxide film layer, Step (6) implant dopants into said n-well to provide graded source/drain junctions for PMOS and NMOS transistor devices, respectively, Step (7) open the surfaces of said source/drain regions for silicide formation wherein said gate element is protected from said silicide by said oxide film insulator layer formed in step (5), Step (8) form a lightly doped silicon film over said silicide, gate oxide and isolation regions wherein said lightly doped silicon film is deposited in polycrystalline structure and recrystallized by beam annealing, Step (9) define the NMOS type transistor device active area and grow thin NMOS gate oxide, Step (10) adjust channel threshold voltages by an impurity implant, Step (11) deposit polysilicon NMOS type transistor device gate material and pattern, Step (12) form oxide spacer regions on said NMOS gate electrode edges, Step (13) implant dopants to obtain source/drain junctions for a transfer device and grow oxide to cover the device.