Selective asperity definition technique suitable for use in fabricating floating-gate transistor

Claim 1

A method in which a first patterned layer of nonmonocrystalline semiconductor material is created on a substructure along its upper surface, characterized by the steps of: performing a thermal oxidation to grow a main electrically insulating layer of oxide along the first patterned layer in such a way that the upper lateral edge of the remainder of the first patterned layer forms an asperity that protrudes outward, the thickness of the insulating layer along the asperity being less than the average thickness of the insulating layer; forming a blanket layer over the insulating layer and over adjoining material of the substructure; and selectively etching the blanket, insulating, and patterned layers with a primary etchant that attacks the material of the blanket and patterned layers more than the material of the insulating layer in order to remove (1) substantially the entire thickness of a specified section of the blanket layer located above the first patterned layer, (2) at least part of the underlying exposed section of the insulating layer including the portion located along the upper surface of the underlying part of the asperity, and (3) largely all of the underlying part of the asperity, whereby the remainder of the blanket layer forms a second patterned layer located above the remainder of the asperity.

Claim 2

A method in which a first patterned layer of nonmonocrystalline semiconductor material is created on a substructure along its upper surface, characterized by the steps of: performing a thermal oxidation to grow a main electrically insulating layer of oxide along the first patterned layer in such a way that the upper lateral edge of the remainder of the first patterned layer forms an asperity that protrudes outward, the thickness of the insulating layer along the asperity being less than the average thickness of the insulating layer; forming a blanket layer over the insulating layer and over adjoining material of the substructure; and selectively etching the blanket, insulating, and patterned layers with a primary etchant that attacks the material of the blanket and patterned layers more than the material of the insulating layer in order to remove (1) substantially the entire thickness of a specified section of the blanket layer located above the first patterned layer, (2) at least part of the underlying exposed section of the insulating layer including the portion located along the upper surface of the underlying part of the asperity, and (3) largely all of the underlying part of the asperity, whereby the remainder of the blanket layer forms a second patterned layer located above the remainder of the asperity.

Claim 14

A method in which a gate dielectric layer is formed along part of the upper surface of a monocrystalline semiconductor substrate of a first conductivity type, and a first patterned layer of nonmonocrystalline semiconductor material is created over a section of the dielectric layer, characterized by the steps of: performing a thermal oxidation to grow a main electrically insulating layer along the first patterned layer in such a way that the upper lateral edge of the remainder of the first patterned layer forms an asperity that protrudes outward, the thickness of the main insulating layer along the asperity being less than the average thickness of the main insulating layer; forming a blanket layer over the main insulating layer and the dielectric layer; selectively etching the blanket layer, the main insulating layer, and the first patterned layer with a primary etchant that attacks the material of the blanket and first patterned layers more than the material of the main insulating layer in order to remove (1) substantially the entire thickness of a specified section of the blanket layer located above the first patterned layer, (2) at least part of the underlying exposed section of the main insulating layer including the portion located along the upper surface of the underlying part of the asperity, and (3) largely all of the underlying part of the asperity, whereby the remainder of the blanket layer forms a second patterned layer located above the remainder of the asperity; providing a further electrically insulating layer along the second patterned layer and along the part of the remainder of the first patterned layer not covered by the second patterned layer in such a way as to significantly inhibit further asperity formation along the upper lateral edge of the remaining portion of the first patterned layer; forming an additional patterned layer over a portion of the further insulating layer located directly above at least part of the remaining portion of the first patterned layer; and forming laterally separated source and drain regions of a second conductivity type opposite to the first conductivity type in the substrate along its then-existing upper surface, the remaining material of the patterned layers being electrically conductive.

Claim 15

A method in which a gate dielectric layer is formed along part of the upper surface of a monocrystalline semiconductor substrate of a first conductivity type, and a first patterned layer of nonmonocrystalline semiconductor material is created over a section of the dielectric layer, characterized by the steps of: performing a thermal oxidation to grow a main electrically insulating layer along the first patterned layer in such a way that the upper lateral edge of the remainder of the first patterned layer forms an asperity that protrudes outward, the thickness of the main insulating layer along the asperity being less than the average thickness of the main insulating layer; forming a blanket layer over the main insulating layer and the dielectric layer; selectively etching the blanket layer, the main insulating layer, and the first patterned layer with a primary etchant that attacks the material of the blanket and first patterned layers more than the material of the main insulating layer in order to remove (1) substantially the entire thickness of a specified section of the blanket layer located above the first patterned layer, (2) at least part of the underlying exposed section of the main insulating layer including the portion located along the upper surface of the underlying part of the asperity, and (3) largely all of the underlying part of the asperity, whereby the remainder of the blanket layer forms a second patterned layer located above the remainder of the asperity; providing a further electrically insulating layer along the second patterned layer and along the part of the remainder of the first patterned layer not covered by the second patterned layer in such a way as to significantly inhibit further asperity formation along the upper lateral edge of the remaining portion of the first patterned layer; forming an additional patterned layer over a portion of the further insulating layer located directly above at least part of the remaining portion of the first patterned layer; and forming laterally separated source and drain regions of a second conductivity type opposite to the first conductivity type in the substrate along its then-existing upper surface, the remaining material of the patterned layers being electrically conductive.

Claim 17

A method in which a field region of electrically insulating material is formed along part of the upper surface of a monocrystalline semiconductor substrate of a first conductivity type, a gate dielectric layer which is much thinner than the field region is formed along another part of the upper surface of the substrate so as to adjoin the field region, and a first patterned layer of nonmonocrystalline semiconductor material is created over a section of the dielectric layer and over an adjoining section of the field region, characterized by the steps of: performing a thermal oxidation to grow a main electrically insulating layer of oxide along the first patterned layer in such a way that the upper lateral edge of the remainder of the first patterned layer forms an asperity that protrudes outward, the thickness of the main insulating layer along the asperity being less than the average thickness of the main insulating layer; forming a blanket layer of nonmonocrystalline semiconductor material over the main insulating layer, the field region, and the dielectric layer; selectively etching the blanket layer, the main insulating layer, and the first patterned layer with a primary etchant that attacks the nonmonocrystalline semiconductor material more than the oxide in order to remove (1) all of the blanket layer located above the first patterned layer except for at least one portion also located above the field region, (2) at least part of the underlying exposed section of the main insulating layer including the portion located along the upper surface of the underlying part of the asperity, and (3) largely all of the underlying part of asperity, whereby the remainder of the blanket layer forms a second patterned layer of nonmonocrystalline semiconductor material located above the remainder of the asperity; providing a further electrically insulating layer along the second patterned layer and along the part of the remainder of the first patterned layer not covered by the second patterned layer in such a way as to significantly inhibit further asperity formation along the upper lateral edge of the remaining portion of the first patterned layer; forming an additional patterned layer of metallic or nonmonocrystalline semiconductor material over a portion of the further insulating layer located directly above at least part of the remaining portion of the first patterned layer; and forming laterally separated source and drain regions of a second conductivity type opposite to the first conductivity type in the substrate along its then-existing upper surface, the remaining material of the patterned layers being electrically conductive.

Claim 18

A method in which a field region of electrically insulating material is formed along part of the upper surface of a monocrystalline semiconductor substrate of a first conductivity type, a gate dielectric layer which is much thinner than the field region is formed along another part of the upper surface of the substrate so as to adjoin the field region, and a first patterned layer of nonmonocrystalline semiconductor material is created over a section of the dielectric layer and over an adjoining section of the field region, characterized by the steps of: performing a thermal oxidation to grow a main electrically insulating layer of oxide along the first patterned layer in such a way that the upper lateral edge of the remainder of the first patterned layer forms an asperity that protrudes outward, the thickness of the main insulating layer along the asperity being less than the average thickness of the main insulating layer; forming a blanket layer of nonmonocrystalline semiconductor material over the main insulating layer, the field region, and the dielectric layer; selectively etching the blanket layer, the main insulating layer, and the first patterned layer with a primary etchant that attacks the nonmonocrystalline semiconductor material more than the oxide in order to remove (1) all of the blanket layer located above the first patterned layer except for at least one portion also located above the field region, (2) at least part of the underlying exposed section of the main insulating layer including the portion located along the upper surface of the underlying part of the asperity, and (3) largely all of the underlying part of asperity, whereby the remainder of the blanket layer forms a second patterned layer of nonmonocrystalline semiconductor material located above the remainder of the asperity; providing a further electrically insulating layer along the second patterned layer and along the part of the remainder of the first patterned layer not covered by the second patterned layer in such a way as to significantly inhibit further asperity formation along the upper lateral edge of the remaining portion of the first patterned layer; forming an additional patterned layer of metallic or nonmonocrystalline semiconductor material over a portion of the further insulating layer located directly above at least part of the remaining portion of the first patterned layer; and forming laterally separated source and drain regions of a second conductivity type opposite to the first conductivity type in the substrate along its then-existing upper surface, the remaining material of the patterned layers being electrically conductive.