Electrically programmable and electrically erasable MOS memory cell

Claim 2

An electrically programmable and erasable MOS storage device disposed on a substrate comprising: spaced-apart source and drain regions in said substrate defining a channel; a floating gate disposed above said channel; a first gate disposed above said channel and said floating gate; a second gate disposed over at least a portion of said floating gate and spaced-apart from said first gate; said floating gate having a surface texture with radii of curvature between 25A and 75A for providing an enhanced electric field between said floating gate and said second gate such that electrons from said floating gate may be transferred to said second gate; whereby, by the application of potentials to said first gate and said drain region charge may be injected into said floating gate and whereby, by the application of a potential to said second gate charge may be removed from said floating gate.

Claim 3

The MOS storage device defined by claim 1 wherein said floating gate comprises polycrystalline silicon.

Claim 4

The MOS storage device defined by claim 2 wherein second gate comprises polycrystalline silicon.

Claim 5

The MOS storage device defined by claim 1 wherein said floating gate is an L-shaped member.

Claim 6

The MOS storage device defined by claim 1 wherein said floating gate is a T-shaped member.

Claim 7

In an MOS storage device which includes a floating gate for storing an electrical charge, a first gate employed for including charge into said floating gate and a second gate spaced-apart from said first gate, employed for removing charge from said floating gate; an improvement for enhancing an electric field between said floating gate and said second gate such that charge may be removed from said floating gate comprising: a surface texture on said floating gate having radii of curvature between 25A and 75A which cause a non-uniform distribution of the electric field between said second gate and floating gate such that regions of high electric field intensity are present; whereby charge may be transferred from said floating gate to said second gate.

Claim 8

In an MOS storage device which includes a floating gate for storing an electrical charge, a first gate employed for including charge into said floating gate and a second gate spaced-apart from said first gate, employed for removing charge from said floating gate; an improvement for enhancing an electric field between said floating gate and said second gate such that charge may be removed from said floating gate comprising: a surface texture on said floating gate having radii of curvature between 25A and 75A which cause a non-uniform distribution of the electric field between said second gate and floating gate such that regions of high electric field intensity are present; whereby charge may be transferred from said floating gate to said second gate.

Claim 9

The MOS storage device of claim 6 wherein said floating gate comprises polycrystalline silicon.

Claim 10

An electrically programmable and electrically erasable memory array which includes a plurality of memory cells disposed on a silicon substrate comprising: source and drain regions defining a plurality of generally parallel spaced-apart channels; a first polycrystalline silicon line disposed transverse to said channels and above said channels, said first line defining gates for selection transistors for said cells; a second polycrystalline silicon line disposed transverse to said channels and above said channels spaced-apart from said first silicon line, said second line defining programming gates for said cells; a third pollycrystalline silicon line disposed transverse to said channels and above said channels spaced-apart from said first and second silicon lines, said third line defining erasing gates for said cells; a plurality of polycrystalline silicon floating gates, one of said gates for each of said cells, each of said floating gates disposed above one of said channels under said second line and extending under said third line; said gloating gates having a surface texture with radii of curvature between 25A and 75A for providing an enhanced electric field between said floating gates and said third line such that electrons from said floating gates may be transferred to said third line; whereby each of said cells in said array may be electrically charged and electrically erased.

Claim 11

An electrically programmable and electrically erasable memory array which includes a plurality of memory cells disposed on a silicon substrate comprising: source and drain regions defining a plurality of generally parallel spaced-apart channels; a first polycrystalline silicon line disposed transverse to said channels and above said channels, said first line defining gates for selection transistors for said cells; a second polycrystalline silicon line disposed transverse to said channels and above said channels spaced-apart from said first silicon line, said second line defining programming gates for said cells; a third pollycrystalline silicon line disposed transverse to said channels and above said channels spaced-apart from said first and second silicon lines, said third line defining erasing gates for said cells; a plurality of polycrystalline silicon floating gates, one of said gates for each of said cells, each of said floating gates disposed above one of said channels under said second line and extending under said third line; said gloating gates having a surface texture with radii of curvature between 25A and 75A for providing an enhanced electric field between said floating gates and said third line such that electrons from said floating gates may be transferred to said third line; whereby each of said cells in said array may be electrically charged and electrically erased.

Claim 12

The array defined by claim 8 wherein said floating gates include L-shaped gates and T-shaped gates.

Claim 13

The array defined by claim 8 wherein said first line and said floating gates are defined by a first silicon layer and wherein said second and third lines are defined by a second silicon layer.

Claim 14

The array defined by claim 8 including a drain contact disposed at one end of each of said channels.

Claim 15

The array defined by claim 11 wherein said cells employ a common source region.