US3825945A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect semiconductor memory apparatus with a floating gate
Assignee: Toshiba Corp
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Filing: 1973-02-27
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Granted: 1974-07-23
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Expires: 1993-02-27
Abstract
Abstract A field effect semiconductor memory apparatus with a floating gate which is so constructed that when a gate electrode is impressed with voltage, there is created across the floating gate and substrate an electric field stronger than, or at least as strong as, that prevailing across the floating gate and gate electrode, whereby the floating gate is stored with information by being impressed with a relatively low level of voltage and the stored information is extinguished by giving rise to an avalanche breakdown across the substrate and at least either of the source and drain.
Inventors
- 👤 F Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
150 words
A field effect semiconductor memory apparatus comprising: a semiconductor substrate of a first conductivity type; a plurality of regions spatially formed in the semiconductor substrate and being of a second conductivity type opposite to that of the semiconductor substrate to form a channel therebetween; an insulation layer formed on the upper surface of the semiconductor substrate so as to bridge said plurality of regions, said insulation layer having a recess opposing said channel; a control gate electrode formed on a portion of the upper surface of the insulation layer including the surface of said recess; and a floating gate electrode disposed within said insulation layer substantially in parallel with said control gate electrode with the control gate electrode overlapping the floating gate electrode, such that the capacitance defined between the control electrode and the floating gate electrode is larger than that defined between the floating gate electrode and the channel.
Claim 2
Dependent Claim
150 words
A field effect semiconductor memory apparatus comprising: a semiconductor substrate of a first conductivity type; a plurality of regions spatially formed in the semiconductor substrate and being of a second conductivity type opposite to that of the semiconductor substrate to form a channel therebetween; an insulation layer formed on the upper surface of the semiconductor substrate so as to bridge said plurality of regions, said insulation layer having a recess opposing said channel; a control gate electrode formed on a portion of the upper surface of the insulation layer including the surface of said recess; and a floating gate electrode disposed within said insulation layer substantially in parallel with said control gate electrode with the control gate electrode overlapping the floating gate electrode, such that the capacitance defined between the control electrode and the floating gate electrode is larger than that defined between the floating gate electrode and the channel.
Claim 3
Dependent Claim
44 words
A field effect semiconductor memory apparatus according to claim 1 wherein the dielectric constant of the insulation material disposed between said control electrode and floating gate electrode is larger than that of the insulation material disposed between said floating gate electrode and the channel.
Claim 4
Dependent Claim
25 words
A field effect semiconductor memory apparatus according to claim 1 wherein said control gate electrode and floating gate electrode have substantially the same general profile.
Claim 5
Dependent Claim
43 words
A field effect semiconductor memory apparatus aCcording to claim 1 wherein said control gate electrode and floating gate electrode each have projections extending beyond said recess, said projections being substantially in parallel with each other and with the upper surface of said substrate.
Claim 6
Dependent Claim
59 words
A field effect semiconductor memory apparatus according to claim 1 wherein, in the area opposing said channel, the distance between the upper surface of said substrate and the lower surface of said floating gate electrode is substantially equal to the distance between the upper surface of said floating gate electrode and the lower surface of said control gate electrode.
Claim 7
Dependent Claim
93 words
A field effect semiconductor memory apparatus according to claim 5 wherein said control gate electrode and floating gate electrode each have projections extending beyond said recess, said projections being substantially in parallel with each other and with the upper surface of said substrate; the distance between the lower surface of the projections of said floating gate electrode and the upper surface of said substrate being greater than the distance between the upper surface of the projections of said floating gate electrode and the lower surface of the projections of said control gate electrode.
Claim 8
Dependent Claim
168 words
A field effect semiconductor memory apparatus comprising: a semiconductor substrate of a first conductivity type; first and second regions spatially formed in the semiconductor substrate and being of a second conductivity type opposite to that of the semiconductor substrate to form a channel therebetween; a first insulation layer of a first dielectric material formed on the upper surface of the semiconductor material so as to bridge said first and second regions; a floating gate electrode provided on said first insulation layer; a second insulation layer positioned on the floating gate electrode bridging the floating gate electrode and the first insulation layer and having substantially the same thickness as that of the first layer, the dielectric constant of the second insulation layer being larger than that of the first insulation layer; and a control gate electrode mounted on the second insulation layer, such that the capacitance defined between the control electrode and the floating gate electrode is larger than that defined between the floating gate electrode and the channel.
Claim 9
Dependent Claim
168 words
A field effect semiconductor memory apparatus comprising: a semiconductor substrate of a first conductivity type; first and second regions spatially formed in the semiconductor substrate and being of a second conductivity type opposite to that of the semiconductor substrate to form a channel therebetween; a first insulation layer of a first dielectric material formed on the upper surface of the semiconductor material so as to bridge said first and second regions; a floating gate electrode provided on said first insulation layer; a second insulation layer positioned on the floating gate electrode bridging the floating gate electrode and the first insulation layer and having substantially the same thickness as that of the first layer, the dielectric constant of the second insulation layer being larger than that of the first insulation layer; and a control gate electrode mounted on the second insulation layer, such that the capacitance defined between the control electrode and the floating gate electrode is larger than that defined between the floating gate electrode and the channel.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-22 | 1978-01-21 | 1978-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-22 | 1982-01-21 | 1982-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-22 | 1986-01-21 | 1986-07-23 | $7700.00 | Window Closed / Lapsed |