US3774087A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory elements
Assignee: Plessey Handel und Investments AG
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Filing: 1972-12-08
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Granted: 1973-11-20
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Expires: 1992-12-08
Abstract
Abstract A memory element which is an improved version of the known FAMOS (floating avalanche-injection metal-oxide-silicon) memory elements in that memory erasure is effected electrically. The structure of the known FAMOS memory elements is modified by having at least one diffused region in the silicon substrate which is isolated from the elements gate and drain electrodes, which is of opposite conductivity type to the substrate, and which is situated adjacent to the channel region between the gate and drain electrodes. At least one region of the substrate situated adjacent to the channel region is also isolated from the gate and drain electrodes, the buried gate of the FAMOS structure partially overlaps these isolated regions and a second gate is provided on the surface of the dielectric layer of the FAMOS structure such that it is above and completely overlaps the silicon gate.
Inventors
- 👤 M Pepper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686; H10D99/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
213 words
A memory element including a silicon substrate of a first conductivity type having first and second spaced-apart regions of a second conductivity type formed in a major surface thereof such that a channel region of the first conductivity type is provided therebetween, at least one region of the substrate situated adjacent to the channel region being isolated from the first and second regions; at least one other region of the second conductivity type formed in the said major surface adjacent to the channel region, the said one other region being isolated from the first and second regions; a dielectric layer formed on the said major surface such that it covers the first and second regions, the said one other region and the isolated substrate region; a silicon gate buried within the dielectric layer such that it is substantiall/ parallel to, and electrically isolated from, the said major surface, the silicon gate partially overlapping each of the first and second regions, the said one other region and the isolated substrate region; a first electrode formed on the surface of the dielectrical layer such that it is above and completely overlaps the silicon gate; and second and third electrodes which are each in electrical contact with a separate one of the first and second regions.
Claim 2
Dependent Claim
213 words
A memory element including a silicon substrate of a first conductivity type having first and second spaced-apart regions of a second conductivity type formed in a major surface thereof such that a channel region of the first conductivity type is provided therebetween, at least one region of the substrate situated adjacent to the channel region being isolated from the first and second regions; at least one other region of the second conductivity type formed in the said major surface adjacent to the channel region, the said one other region being isolated from the first and second regions; a dielectric layer formed on the said major surface such that it covers the first and second regions, the said one other region and the isolated substrate region; a silicon gate buried within the dielectric layer such that it is substantiall/ parallel to, and electrically isolated from, the said major surface, the silicon gate partially overlapping each of the first and second regions, the said one other region and the isolated substrate region; a first electrode formed on the surface of the dielectrical layer such that it is above and completely overlaps the silicon gate; and second and third electrodes which are each in electrical contact with a separate one of the first and second regions.
Claim 3
Dependent Claim
80 words
A memory element as claimed in claim 1 wherein the element includes two regions of the second conductivity type formed in the said major surface on opposite sides of the channel region, the two regions being partially overlapped by the silicon gate and isolated from the first and second regions and wherein two regions of the substrate situated on opposite sides of the channel region are isolated from the first and second regions and partially overlapped by the silicon gate.
Claim 4
Dependent Claim
35 words
A memory element as claimed in claim 1 wherein each of the isolated regions is surrounded in the substrate by an oxide layer to effect isolation of the region from the first and second regions.
Claim 5
Dependent Claim
18 words
A memory element as claimed in claim 3 wherein each of the oxide layers is of silicon dioxide.
Claim 6
Dependent Claim
57 words
A memory element as claimed in claim 1 wherein the thickness of those sections of the dielectric layer which are contiguous with the edges of each of the isolated regions is greater than the thickness of the remainder of the dielectric layer by an amount which effects isolation of the regions from the first and second regions.
Claim 7
Dependent Claim
24 words
A memory element as claimed in claim 1 wherein the first conductivity type is n-type and wherein the second conductivity type is p+ type.
Claim 8
Dependent Claim
213 words
A memory element including a silicon substrate of a first conductivity type having first and second spaced apart regions of a second conductivity type formed in a major surface thereof such that a channel region of the first conductivity type is provided therebetween, two regions of the substrate situated one on each side of the channel region being isolated from the first and second regions; third and fourth regions of the second conductivity type formed in the said major surface and situated one on each side of the channel region, the third and fourth regions being isolated from the first and second regions; a dielectric layer formed on the said major surface such that it covers the first second third and fourth regions and isolated substrate regions; a silicon gate buried within the dielectric layer such that it is substantially parallel to, and electrically isolated from, the said major surface, the silicon gate partially overlapping each of the first second second third and fourth regions and the isolated substrate regions; a first electrode formed on the surface of the dielectric layer such that it is above and completely overlaps the silicon gate; and second and third electrodes which are each in electrical contact with a separate one of the first and second regions.
Claim 9
Dependent Claim
213 words
A memory element including a silicon substrate of a first conductivity type having first and second spaced apart regions of a second conductivity type formed in a major surface thereof such that a channel region of the first conductivity type is provided therebetween, two regions of the substrate situated one on each side of the channel region being isolated from the first and second regions; third and fourth regions of the second conductivity type formed in the said major surface and situated one on each side of the channel region, the third and fourth regions being isolated from the first and second regions; a dielectric layer formed on the said major surface such that it covers the first second third and fourth regions and isolated substrate regions; a silicon gate buried within the dielectric layer such that it is substantially parallel to, and electrically isolated from, the said major surface, the silicon gate partially overlapping each of the first second second third and fourth regions and the isolated substrate regions; a first electrode formed on the surface of the dielectric layer such that it is above and completely overlaps the silicon gate; and second and third electrodes which are each in electrical contact with a separate one of the first and second regions.
References Cited (Backward Citations)
US3728695A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-19 | 1977-05-21 | 1977-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-19 | 1981-05-21 | 1981-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-19 | 1985-05-21 | 1985-11-20 | $7700.00 | Window Closed / Lapsed |