Semiconductor integrated circuit device and method of manufacturing the same

Claim 1

a method of fabricating a semiconductor memory device, including: a memory array portion formed on a semiconductor substrate at a first location of one main surface thereof and including a plurality of MIS memory transistors, said MIS memory transistors being respectively formed at first areas of said first location and each having a floating gate electrode and a control gate electrode overlying said floating gate electrode; and a peripheral circuit portion formed at a second location of said semiconductor substrate different from said first location in association with said memory array portion and including a plurality of MIS transistors and wiring lines, said MIS transistors being respectively formed at second areas of said second location and each having a gate electrode, comprising the steps of: forming a first insulating film on said semiconductor substrate at said first location and said second location; forming a first layer of conductive material on said first insulating film at said first location and said second location; patterning said first layer of conductive material on said first insulating film at said second location so as to form at least some of said gate electrodes; forming a second insulating film on said first layer of conductive material; forming a second layer of conductive material on said second insulating film at said first location and at said second location; patterning said second layer of conductive material, said second insulating film, said first layer of conductive material and said first insulating film at said first location using a photoresist film as a mask so as to form said control gate electrode and said floating gate electrode of said memory array portion; and patterning said second layer of conductive material at said second location.

Claim 2

a method of fabricating a semiconductor memory device, including: a memory array portion formed on a semiconductor substrate at a first location of one main surface thereof and including a plurality of MIS memory transistors, said MIS memory transistors being respectively formed at first areas of said first location and each having a floating gate electrode and a control gate electrode overlying said floating gate electrode; and a peripheral circuit portion formed at a second location of said semiconductor substrate different from said first location in association with said memory array portion and including a plurality of MIS transistors and wiring lines, said MIS transistors being respectively formed at second areas of said second location and each having a gate electrode, comprising the steps of: forming a first insulating film on said semiconductor substrate at said first location and said second location; forming a first layer of conductive material on said first insulating film at said first location and said second location; patterning said first layer of conductive material on said first insulating film at said second location so as to form at least some of said gate electrodes; forming a second insulating film on said first layer of conductive material; forming a second layer of conductive material on said second insulating film at said first location and at said second location; patterning said second layer of conductive material, said second insulating film, said first layer of conductive material and said first insulating film at said first location using a photoresist film as a mask so as to form said control gate electrode and said floating gate electrode of said memory array portion; and patterning said second layer of conductive material at said second location.