Abstract A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer. The first, second and third epitaxial layers are in contact with a polycrystalline silicon layer containing impurities of the second conductivity type. The first conductivity type is opposite to the second conductivity type.
A method for producing a semiconductor memory device having a plurality of trench capacitors and a plurality of switching transistors electrically connected to said trench capacitors, comprising the steps of: forming a plurality of trenches in a semiconductor substrate of a first conductivity type; forming a capacitor insulating film on the side portion of each of said trenches; filling said trenches with electrically conductive materials containing impurities of the first conductivity type; covering the upper face of each of said electrically conductive materials embedded in the trenches with an insulating film having an opening therein; growing a first epitaxial layer of the first conductivity type on said insulating film by the lateral epitaxial growth technique, said first epitaxial layer acting as a source region of each of said switching transistors; growing a second epitaxial layer of a second conductivity type on said first epitaxial layer, said second conductivity type being opposite to the first conductivity type and said second epitaxial layer acting as a channel region of each of said switching transistors; growing a third epitaxial layer of the first conductivity type on said second epitaxial layer, said third epitaxial layer acting as a drain region of each of said switching transistors; and forming a polycrystalline silicon layer containing impurities of the second conductivity type on said semiconductor substrate, the polycrystalline silicon layer being in contact with said first, second and third epitaxial layers.
Claim 2
Independent Claim
234 words
A method for producing a semiconductor memory device having a plurality of trench capacitors and a plurality of switching transistors electrically connected to said trench capacitors, comprising the steps of: forming a plurality of trenches in a semiconductor substrate of a first conductivity type; forming a capacitor insulating film on the side portion of each of said trenches; filling said trenches with electrically conductive materials containing impurities of the first conductivity type; covering the upper face of each of said electrically conductive materials embedded in the trenches with an insulating film having an opening therein; growing a first epitaxial layer of the first conductivity type on said insulating film by the lateral epitaxial growth technique, said first epitaxial layer acting as a source region of each of said switching transistors; growing a second epitaxial layer of a second conductivity type on said first epitaxial layer, said second conductivity type being opposite to the first conductivity type and said second epitaxial layer acting as a channel region of each of said switching transistors; growing a third epitaxial layer of the first conductivity type on said second epitaxial layer, said third epitaxial layer acting as a drain region of each of said switching transistors; and forming a polycrystalline silicon layer containing impurities of the second conductivity type on said semiconductor substrate, the polycrystalline silicon layer being in contact with said first, second and third epitaxial layers.
Claim 3
Dependent Claim
36 words
A method according to claim 1, further comprising the step of: forming a well of the second conductivity type in a surface portion of said semiconductor substrate which is in contact with said polycrystalline silicon layer.