Abstract Dynamic random access memory (DRAM) devices are taught wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO 2 /Si 3 N 4 /SiO 2 is provided for the capacitor storage insulator. A thin layer of SiO 2 is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO 2 layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.
A method for fabricating a dynamic memory cell having a single-crystal transistor device on a trench capacitor structure comprising the steps of Step 1. forming a mask layer on a single-crystal silicon substrate; Step 2. opening a window in said mask layer and etching a trench in said substrate beneath said window; Step 3. filling said trench with polysilicon material and doping said polysilicon material; Step 4. forming a layer of oxide over said polysilicon filled trench; Step 5. removing said mask layer from said substrate; Step 6. growing a doped epitaxial single-crystal silicon layer over said substrate and oxide covered trench regions; Step 7. forming a mask layer over said epitaxial silicon layer; Step 8. opening a window in said mask layer over said trench region and etching away said epitaxial silicon and oxide over said trench; Step 9. refilling said window formed in step 8 with polysilicon material; Step 10. removing said mask layer formed in step 7; Step 11. forming an access transistor device over said trench by conventional gate oxide growth and definition, and source/drain dopant implantation.
Claim 2
Independent Claim
181 words
A method for fabricating a dynamic memory cell having a single-crystal transistor device on a trench capacitor structure comprising the steps of Step 1. forming a mask layer on a single-crystal silicon substrate; Step 2. opening a window in said mask layer and etching a trench in said substrate beneath said window; Step 3. filling said trench with polysilicon material and doping said polysilicon material; Step 4. forming a layer of oxide over said polysilicon filled trench; Step 5. removing said mask layer from said substrate; Step 6. growing a doped epitaxial single-crystal silicon layer over said substrate and oxide covered trench regions; Step 7. forming a mask layer over said epitaxial silicon layer; Step 8. opening a window in said mask layer over said trench region and etching away said epitaxial silicon and oxide over said trench; Step 9. refilling said window formed in step 8 with polysilicon material; Step 10. removing said mask layer formed in step 7; Step 11. forming an access transistor device over said trench by conventional gate oxide growth and definition, and source/drain dopant implantation.
Claim 3
Dependent Claim
45 words
A method according to claim 1 wherein said epitaxial layer grown in Step 6 is grown from single-crystal seeds from said single-crystal substrate to provide a single-crystal epitaxial layer, and wherein said access transistor device formed in Step 11 is composed of said single-crystal material.
Claim 4
Dependent Claim
17 words
A method according to claim 2 wherein said single-crystal silicon substrate is a heavily p+ doped wafer.
Claim 5
Dependent Claim
25 words
A method according to claim 2 wherein said single-crystal substrate further includes a p- epitaxial layer disposed on top of said heavily p+ doped wafer.
Claim 6
Dependent Claim
24 words
A method according to claim 2 wherein said mask layer formed in Step 1 is a composite layer of silicon oxide and silicon nitride.
Claim 7
Dependent Claim
53 words
A method according to claim 2 wherein a composite layer of silicon oxide and silicon nitride on silicon oxide is formed on the surfaces of the trench etched in Step 2 prior to filling said trench with polysilicon material in Step 3, said composite layer providing an insulation layer for trench capacitor storage.
Claim 8
Dependent Claim
42 words
A method according to claim 2 wherein said access transistor from Step 11 further includes heavily doping said polysilicon material refilled in Step 9 for providing a connection from the source of said access transistor to said polysilicon material in said trench.