Vertical type mos dynamic memory cell

Abstract

Abstract PURPOSE:To reduce the software error production rate due to alpha-ray by integrating a vertical one-transistor MOS memory of the structure exposed on the surface of a substrate only at the upper end of a cylindrical gate, thereby enhancing the integration. CONSTITUTION:An N<+> type layer 2 is formed to produce lattice defects of high density on a P<+> type Si substrate 1, and a P<+> type layer 3 is formed by epitaxial growth. The epitaxial layer on the layer 2 becomes an N<+> type polycrystalline layer 4 on the layer 2. Further, a P<-> type layer 6 and an N<+> type layer 7 are formed thereon, a cylindrical hole reaching the layer 4 is formed, and a gate electrode 8 is formed through an insulating layer 5'. Thus, a vertical MOSFET having a cylindrical gate electrode 8, the layer 4 as a source or drain and the layer 7 as a drain or source can be obtained. The layer 4 becomes one electrode of a charge storage capacitor. In this manner the integration is improved, and the software error due to alpha-ray can be reduced.

Inventors

• 👤 Yuji Furumura
• 👤 雄二 古村

Bibliographic Details