US4397075A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FET Memory cell structure and process
Assignee: International Business Machines Corp
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Filing: 1980-07-03
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Granted: 1983-08-09
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Expires: 2000-07-03
Abstract
Abstract A dense, vertical MOS FET memory cell has a high charge storage capacitance per unit area of substrate surface. The charge storage capacitor structure is formed within a well etched in the silicon semiconductor substrate by a combination of reactive ion etching and a self-limiting wet etch.
Inventors
- 👤 Joseph J. Fatula, Jr.
- 👤 Paul L. Garbarino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:42
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/30; H10B12/37; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P50/60; H10P50/64; H10P50/642; H10P50/644
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
147 words
A method for producing a dense MOS FET memory device having a vertical capacitor comprising providing a monocrystalline silicon substrate having a gate including a gate dielectric layer on said substrate, a gate electrode layer on said dielectric layer and source and drain regions in said substrate on opposite sides of said gate; reactive ion etching a substantially U-shaped opening into said substrate in said drain region adjacent to said gate; growing a silicon dioxide layer on the surface of said U-shaped opening; reactive ion etching said U-shaped opening deeper into said substrate to form a deeper U-shaped opening; etching said deeper opening with a directional etchant to form a well having an enlarged buried opening; removing by etching said silicon dioxide from said well; diffusing an impurity into the surfaces of said well and; forming electrical contacts to the source and to said gate electrode layer.
Claim 2
Independent Claim
147 words
A method for producing a dense MOS FET memory device having a vertical capacitor comprising providing a monocrystalline silicon substrate having a gate including a gate dielectric layer on said substrate, a gate electrode layer on said dielectric layer and source and drain regions in said substrate on opposite sides of said gate; reactive ion etching a substantially U-shaped opening into said substrate in said drain region adjacent to said gate; growing a silicon dioxide layer on the surface of said U-shaped opening; reactive ion etching said U-shaped opening deeper into said substrate to form a deeper U-shaped opening; etching said deeper opening with a directional etchant to form a well having an enlarged buried opening; removing by etching said silicon dioxide from said well; diffusing an impurity into the surfaces of said well and; forming electrical contacts to the source and to said gate electrode layer.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein the directional etchant is ethylene diamine pyrocatechol.
Claim 4
Dependent Claim
22 words
The method of claim 1 wherein the reactive ion etching of said U-shaped opening is in a fluorine or chlorine containing atmosphere.
Claim 5
Dependent Claim
18 words
The method of claim 1 wherein said substrate is P type silicon and said impurity is N type.
Claim 6
Dependent Claim
10 words
The method of claim 4 wherein said impurity is phosphorus.
Claim 7
Dependent Claim
10 words
The method of claim 4 wherein said impurity is arsenic.
Claim 8
Dependent Claim
21 words
The method of claim 1 wherein said enlarged buried opening has faces lying along the (111) crystal planes of said substrate.
Claim 9
Independent Claim
124 words
A method for producing a vertical capacitor comprising: providing a monocrystalline silicon substrate of a first conductivity type and having a region of a second conductivity type in said substrate; reactive ion etching a substantially U-shaped opening into said substrate into and through said region of second conductivity type; growing a silicon dioxide layer on the surface of said U-shaped opening; reactive ion etching said U-shaped opening deeper into said substrate to form a deeper U-shaped opening; etching said deeper opening with a directional etchant to form a well having an enlarged buried opening; removing by etching said silicon dioxide from said well; diffusing an impurity into the surfaces of said well; and forming electrical contact to the said region of second conductivity type.
Claim 10
Independent Claim
124 words
A method for producing a vertical capacitor comprising: providing a monocrystalline silicon substrate of a first conductivity type and having a region of a second conductivity type in said substrate; reactive ion etching a substantially U-shaped opening into said substrate into and through said region of second conductivity type; growing a silicon dioxide layer on the surface of said U-shaped opening; reactive ion etching said U-shaped opening deeper into said substrate to form a deeper U-shaped opening; etching said deeper opening with a directional etchant to form a well having an enlarged buried opening; removing by etching said silicon dioxide from said well; diffusing an impurity into the surfaces of said well; and forming electrical contact to the said region of second conductivity type.
Claim 11
Dependent Claim
31 words
The method of claim 8 wherein said reactive ion etching of said U-shaped opening is in a fluorine or chlorine containing atmosphere and the said directional etchant is ethylene diamine pyrocatechol.
Claim 12
Dependent Claim
27 words
The method of claim 8 wherein said first conductivity type is P type, said second conductivity type is N type, and said substrate is composed of silicon.
Claim 13
Dependent Claim
25 words
The method of claim 8 wherein said diffusing is done from a phosphosilicate glass layer that has been formed upon the surface of said well.
References Cited (Backward Citations)
US3387286A
Cited
US3977071A
Cited
US3728179A
Cited
US3962713A
Cited
US4017885A
Cited
US4141765A
Cited
US4160987A
Cited
US4139442A
Cited
US4116720A
Cited
US4346513A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-08 | 1987-02-07 | 1987-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-08 | 1991-02-07 | 1991-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-08 | 1995-02-07 | 1995-08-09 | $7700.00 | Window Closed / Lapsed |