Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors

Claim 1

A method for fabricating an integrated circuit containing an array of FETs having recessed field oxide isolation between FETs, and associated FET circuits peripheral to the array of FETs but on the same semiconductive substrate, and wherein FETs of the array have a channel region; a gate insulator; a doped polycrystalline silicone gate self-aligned to the field oxide isolation on the sides of the gate in the width direction, the gate neither overlapping nor underlapping the field oxide isolation; source and drain regions being self-aligned to the ends of the gate in the length direction; insulation over the source and drain but not over the gate; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line which comprises: (A) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (B) providing an insulator layer on said substrate, which insulator layer is to be subsequently delineated to provide the gate insulator; (C) depositing a layer of polycrystalline silicon above the insulator layer; (D) depositing an oxidation barrier layer above said polycrystalline silicon layer; (E) delineating by masking and etching first predetermined polycrystalline silicon regions to provide the device area; (F) growing in the etched regions isolation oxide recessed into the substrate to provide insulating field oxide regions between FETs of the array; (G) delineating by masking and etching second predetermined polycrystalline silicon regions to provide polycrystalline silicon gate regions of the FETs; (H) thermally diffusing or ion implanting active impurities of a second and opposite type into preselected regions of the semiconductive substrate to provide FET source and drain regions; (I) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon FET gates which are still protected by an oxidation barrier layer; (J) removing existing oxidation barrier layer from over the FET gates by use of an etchant; (K) delineating contact holes to provide vias for achieving electrical connection between metallic interconnection lines and FET source and drain regions; (L) depositing and delineating a metallic-type high conductivity electrical interconnection pattern that makes electrical connection to the polycrystalline silicon FET gates; and to FET source and drains; and (M) providing electrical connection to said semiconductive substrate.

Claim 2

A method for fabricating an integrated circuit containing an array of FETs having recessed field oxide isolation between FETs, and associated FET circuits peripheral to the array of FETs but on the same semiconductive substrate, and wherein FETs of the array have a channel region; a gate insulator; a doped polycrystalline silicone gate self-aligned to the field oxide isolation on the sides of the gate in the width direction, the gate neither overlapping nor underlapping the field oxide isolation; source and drain regions being self-aligned to the ends of the gate in the length direction; insulation over the source and drain but not over the gate; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line which comprises: (A) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (B) providing an insulator layer on said substrate, which insulator layer is to be subsequently delineated to provide the gate insulator; (C) depositing a layer of polycrystalline silicon above the insulator layer; (D) depositing an oxidation barrier layer above said polycrystalline silicon layer; (E) delineating by masking and etching first predetermined polycrystalline silicon regions to provide the device area; (F) growing in the etched regions isolation oxide recessed into the substrate to provide insulating field oxide regions between FETs of the array; (G) delineating by masking and etching second predetermined polycrystalline silicon regions to provide polycrystalline silicon gate regions of the FETs; (H) thermally diffusing or ion implanting active impurities of a second and opposite type into preselected regions of the semiconductive substrate to provide FET source and drain regions; (I) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon FET gates which are still protected by an oxidation barrier layer; (J) removing existing oxidation barrier layer from over the FET gates by use of an etchant; (K) delineating contact holes to provide vias for achieving electrical connection between metallic interconnection lines and FET source and drain regions; (L) depositing and delineating a metallic-type high conductivity electrical interconnection pattern that makes electrical connection to the polycrystalline silicon FET gates; and to FET source and drains; and (M) providing electrical connection to said semiconductive substrate.

Claim 28

A method for fabricating an integrated circuit containing an array of FET one-device memory cells having recessed field oxide isolation between cells and associated FET addressing, sensing, decoding, and clocking circuits peripheral to the array of memory cells and wherein memory cells of the array have a channel region; a gate insulator; a doped polycrystalline silicon gate; a charge storage capacitor consisting of a polysilicon upper electrode, a capacitor insulator and a silicon lower electrode beneath the upper electrode; self-alignment between field oxide isolation and the sides of the gate in the width direction, the gate neither overlapping nor underlapping the field oxide isolation; source and drain regions being self-aligned to the ends of the gate in the length direction; insulator over the source and drain but not over the gate; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line which comprises: (A) providing a semiconductive substrate of p-conductive type containing active impurities of p-type; (B) providing insulator layer on said substrate, which insulator layer is to be subsequently delineated to provide the gate insulator; (C) depositing a first layer of polycrystalline silicon above the gate insulator layer; (D) depositing an oxidation barrier layer above said first polycrystalline silicon layer; (E) delineating by masking and etching first predetermined polycrystalline silicon regions to provide the device area; (F) growing in the etched regions isolation oxide recessed into the substrate to provide insulating field oxide regions between memory cells of the array; (G) delineating by masking and etching second predetermined polysilicon regions in said first polysilicon layer to provide polysilicon gate regions of the memory cells; (H) thermally diffusing or ion implanting active impurities of a second and opposite type into preselected regions of the semiconductive substrate to provide FET source regions. FET drain regions, and lower electrodes of the storage capacitors; (I) providing a capacitor insulator; (J) then depositing a second and subsequent layer of polysilicon above the capacitor insulator; (K) then delineating the second and subsequent polysilicon layer to provide predetermined polysilicon upper electrode regions above the corresponding doped lower electrodes of the storage capacitors; (L) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon FET gates which are still protected by an oxidation barrier layer; (M) removing the existing oxidation barrier layer from over the FET gates by use of an etchant; (N) delineating contact holes to provide vias for achieving electrical connection between metallic interconnection lines and polysilicon upper capacitor electrodes; source and drain regions in circuits peripheral to the array of memory cells; (O) depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the polysilicon FET gates in the array of memory cells; to polysilicon upper capacitor electrodes; and to FET sources, gates, and drains in circuits peripheral to the array of memory cells; and (P) providing electrical connection to said semiconductive substrate.

Claim 29

A method for fabricating an integrated circuit containing an array of FET one-device memory cells having recessed field oxide isolation between cells and associated FET addressing, sensing, decoding, and clocking circuits peripheral to the array of memory cells and wherein memory cells of the array have a channel region; a gate insulator; a doped polycrystalline silicon gate; a charge storage capacitor consisting of a polysilicon upper electrode, a capacitor insulator and a silicon lower electrode beneath the upper electrode; self-alignment between field oxide isolation and the sides of the gate in the width direction, the gate neither overlapping nor underlapping the field oxide isolation; source and drain regions being self-aligned to the ends of the gate in the length direction; insulator over the source and drain but not over the gate; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line which comprises: (A) providing a semiconductive substrate of p-conductive type containing active impurities of p-type; (B) providing insulator layer on said substrate, which insulator layer is to be subsequently delineated to provide the gate insulator; (C) depositing a first layer of polycrystalline silicon above the gate insulator layer; (D) depositing an oxidation barrier layer above said first polycrystalline silicon layer; (E) delineating by masking and etching first predetermined polycrystalline silicon regions to provide the device area; (F) growing in the etched regions isolation oxide recessed into the substrate to provide insulating field oxide regions between memory cells of the array; (G) delineating by masking and etching second predetermined polysilicon regions in said first polysilicon layer to provide polysilicon gate regions of the memory cells; (H) thermally diffusing or ion implanting active impurities of a second and opposite type into preselected regions of the semiconductive substrate to provide FET source regions. FET drain regions, and lower electrodes of the storage capacitors; (I) providing a capacitor insulator; (J) then depositing a second and subsequent layer of polysilicon above the capacitor insulator; (K) then delineating the second and subsequent polysilicon layer to provide predetermined polysilicon upper electrode regions above the corresponding doped lower electrodes of the storage capacitors; (L) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon FET gates which are still protected by an oxidation barrier layer; (M) removing the existing oxidation barrier layer from over the FET gates by use of an etchant; (N) delineating contact holes to provide vias for achieving electrical connection between metallic interconnection lines and polysilicon upper capacitor electrodes; source and drain regions in circuits peripheral to the array of memory cells; (O) depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the polysilicon FET gates in the array of memory cells; to polysilicon upper capacitor electrodes; and to FET sources, gates, and drains in circuits peripheral to the array of memory cells; and (P) providing electrical connection to said semiconductive substrate.