Abstract An integrated circuit structure of a field effect transistor (FET) serially connected to a capacitor has the capacitor formed by one of the current flow electrodes of the FET and by a polycrystalline silicon (polysilicon) field shield. The structure includes, in a semiconductor (e.g., silicon) substrate, of, e.g., p-type conductivity, two spaced regions of opposite conductivity type to that of the substrate, e.g., n-type. One of the spaced regions serves as a first plate of the capacitor and as a first current flow electrode of the FET. The other region serves as a second current flow electrode of the FET. A first insulating layer on the substrate has a polysilicon layer on it covering the two spaced regions and is directly and ohmically electrically connected to the substrate. The portion of the polysilicon layer over the spaced region serving as the first plate of the capacitor serves as the second plate of the capacitor. A second insulating layer covers the polysilicon layer and a second layer of conducting material, e.g., aluminum, is provided on the second insulating layer. The second conductive layer overlies the space between the two spaced regions and serves as a gate electrode for the FET. When employed as a memory circuit, the spaced region of opposite conductivity type to the substrate which does not serve as the first plate of the capacitor is desirably a diffused bit/sense line and the second conducting layer serves as a word line.
The integrated circuit of claim 1 in which the said first conducting means is polycrystalline silicon.
Claim 2
Dependent Claim
29 words
The integrated circuit of claim 1 in which the said first conducting means has a direct ohmic connection to the semiconductor substrate and means of applying a reference voltage.
Claim 3
Dependent Claim
19 words
An integrated circuit of claim 1 wherein said insulating layer is a composite of silicon dioxide and silicon nitride.
Claim 4
Dependent Claim
25 words
An integrated circuit of claim 1 wherein said second conducting means is coupled to said gate area through an opening in said first conducting means.
Claim 5
Dependent Claim
208 words
An integrated circuit memory comprising: A. an array of storage cells comprising field effect transistors having a gate area and current flow electrodes of a first conductivity type in a semiconductor substratE of a second conductivity type having an insulating layer thereon, a capacitor series connected to one of the said first conductivity type current flow electrodes and the first conductivity type electrode to which said capacitor is connected serving as a first plate of the capacitor, a first conducting means disposed on said insulating layer forming a field shield over substantially the entire surface of said semiconductor substrate outside said gate area and overlaying a portion of said first conductivity type current flow electrodes area to form a second one of the plates of said capacitor, thereby acting dually as a field shield and capacitor plate, a second conducting means coupled to said gate area and lying in substantially a superimposed plane and insulated from said first conducting means; B. a plurality of bit lines each connected to the current flow electrode of the field effect transistor other than said electrode forming the capacitor plate; and C. a plurality of word lines each connected to said second conducting means of a group of the field effect transistors.
Claim 6
Dependent Claim
26 words
The memory of claim 6 in which said first conducting means dually acting as a capacitor plate and field shield comprises a layer of polycrystalline silicon.
Claim 7
Dependent Claim
34 words
The memory of claim 7 in which the semiconductor substrate is p-type silicon, the spaced apart regions are n-type silicon, and said first conducting means has a direct, ohmic connection to the silicon substrate.