US3720922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Charge coupled memory
Assignee: RCA Corp
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Filing: 1971-03-17
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Granted: 1973-03-13
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Expires: 1991-03-17
Abstract
Abstract A plurality of storage electrodes, extending in the column direction, each electrode coupled to a common semiconductor substrate at spaced regions along its length, each such region comprising a minority carrier storage location. A plurality of digit lines are formed in the substrate, each such line being coupled to a column of locations. These lines serve as sources of minority carriers and as sense lines. A plurality of word lines extending in the row direction are located one over each row of locations. Each word line can be operated to create conduction channels between the digit lines and the storage locations, respectively, along that word line.
Inventors
- 👤 W Kosonocky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:17
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/35; H; H10; H10B; H10B12/00; H10B12/30; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/122
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
175 words
A charge coupled memory comprising, in combination: a semiconductor substrate; a pluRality of storage electrodes, each comprising a conductor insulated from the substrate and extending in the column direction, and each coupled to the substrate only at spaced regions along its length, each region of a storage electrode coupled to the substrate comprising a charge storage location, said locations being arranged in columns and rows; a plurality of digit lines formed in said substrate, each capable of acting as a source of minority charge carriers, each line coupled to a column of said storage locations, each digit line comprising a region in said semiconductor substrate of a conductivity opposite to that of the substrate; and a plurality of word lines, each word line coupled to a row of storage locations, each word line being formed with spaced regions along its length coupled to the substrate for controlling the conduction of minority charge carriers between the respective digit lines and their storage locations along that word line, and each storage electrode passing beneath said word lines.
Claim 2
Dependent Claim
175 words
A charge coupled memory comprising, in combination: a semiconductor substrate; a pluRality of storage electrodes, each comprising a conductor insulated from the substrate and extending in the column direction, and each coupled to the substrate only at spaced regions along its length, each region of a storage electrode coupled to the substrate comprising a charge storage location, said locations being arranged in columns and rows; a plurality of digit lines formed in said substrate, each capable of acting as a source of minority charge carriers, each line coupled to a column of said storage locations, each digit line comprising a region in said semiconductor substrate of a conductivity opposite to that of the substrate; and a plurality of word lines, each word line coupled to a row of storage locations, each word line being formed with spaced regions along its length coupled to the substrate for controlling the conduction of minority charge carriers between the respective digit lines and their storage locations along that word line, and each storage electrode passing beneath said word lines.
Claim 3
Dependent Claim
175 words
A charge coupled memory comprising, in combination: a semiconductor substrate; a pluRality of storage electrodes, each comprising a conductor insulated from the substrate and extending in the column direction, and each coupled to the substrate only at spaced regions along its length, each region of a storage electrode coupled to the substrate comprising a charge storage location, said locations being arranged in columns and rows; a plurality of digit lines formed in said substrate, each capable of acting as a source of minority charge carriers, each line coupled to a column of said storage locations, each digit line comprising a region in said semiconductor substrate of a conductivity opposite to that of the substrate; and a plurality of word lines, each word line coupled to a row of storage locations, each word line being formed with spaced regions along its length coupled to the substrate for controlling the conduction of minority charge carriers between the respective digit lines and their storage locations along that word line, and each storage electrode passing beneath said word lines.
Claim 4
Dependent Claim
175 words
A charge coupled memory comprising, in combination: a semiconductor substrate; a pluRality of storage electrodes, each comprising a conductor insulated from the substrate and extending in the column direction, and each coupled to the substrate only at spaced regions along its length, each region of a storage electrode coupled to the substrate comprising a charge storage location, said locations being arranged in columns and rows; a plurality of digit lines formed in said substrate, each capable of acting as a source of minority charge carriers, each line coupled to a column of said storage locations, each digit line comprising a region in said semiconductor substrate of a conductivity opposite to that of the substrate; and a plurality of word lines, each word line coupled to a row of storage locations, each word line being formed with spaced regions along its length coupled to the substrate for controlling the conduction of minority charge carriers between the respective digit lines and their storage locations along that word line, and each storage electrode passing beneath said word lines.
Claim 5
Dependent Claim
40 words
In a charge coupled memory as set forth in claim 1, further including: means coupled to all of said storage electrodes for applying a direct voltage bias thereto in a sense to produce at each storage location a potential well.
Claim 6
Dependent Claim
75 words
In a charge coupled memory as set forth in claim 2, further including: means coupled to said digit lines for switching them between voltage levels at which they operate as sources and drains, respectively, for minority charge carriers; and means coupled to said word lines for switching them between voltage levels at which they will permit and prevent, respectively, the passage of minority charge carriers between digit lines and storage locations along said word lines.
References Cited (Backward Citations)
US3387286A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-12 | 1976-09-11 | 1977-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-12 | 1980-09-11 | 1981-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-12 | 1984-09-11 | 1985-03-13 | $7700.00 | Window Closed / Lapsed |