US5616934A
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US
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Fully planarized thin film transistor (TFT) and process to fabricate same
Assignee: Micron Technology Inc
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Filing: 1996-03-22
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Granted: 1997-04-01
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Expires: 2016-03-22
Abstract
Abstract The invention is directed to a thin film transistor (TFT) fabricated by using a planarized poly plug as the bottom gate for use in any integrated circuit and in particular an static random access memory (SRAM). The TFT is used in an SRAM device to form a planarized SRAM cell comprising: a pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer having grooves therein, each groove providing access to an underlying conductive material; a planarized conductive plug residing inside each groove, whereby a first conductive plug forms a thin film transistor gate connecting to an to an adjacent inverter and a second conductive plug provides connection to the gate of the pulldown device; a gate dielectric overlying the first planarized conductive plug; and a patterned semiconductive layer doped such that a channel region aligns to each thin film transistor gate and a source/drain region aligns to each side of the channel region is formed.
Inventors
- 👤 Charles H. Dennison
- 👤 Monte Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:38
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10B; H10B10/00; H10B10/12; H10B10/125; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S438/00; Y10S438/964
Claims Analysis
Total Claims: 47
Claim 1
Independent Claim
112 words
A transistor fabricated on a substrate assembly having a conductive region formed therein, comprising: a generally insulating material having an opening therein defined in part by a sidewall, said opening extending from a top surface to said conductive region in said substrate assembly; a conductive silicon material within said opening, said conductive silicon material in physical contact with said sidewall of said insulating material and in electrical contact with said conductive region; a gate dielectric overlying said conductive silicon material; and at least two semiconductor regions defining source and drain areas overlying said gate dielectric, said source and drain areas in operative relation to said conductive silicon material to form said transistor.
Claim 2
Dependent Claim
112 words
A transistor fabricated on a substrate assembly having a conductive region formed therein, comprising: a generally insulating material having an opening therein defined in part by a sidewall, said opening extending from a top surface to said conductive region in said substrate assembly; a conductive silicon material within said opening, said conductive silicon material in physical contact with said sidewall of said insulating material and in electrical contact with said conductive region; a gate dielectric overlying said conductive silicon material; and at least two semiconductor regions defining source and drain areas overlying said gate dielectric, said source and drain areas in operative relation to said conductive silicon material to form said transistor.
Claim 3
Dependent Claim
14 words
The transistor of claim 1, wherein said conductive silicon material comprises conductively doped polysilicon.
Claim 4
Dependent Claim
18 words
The transistor of claim 1, wherein said opening in said generally insulating material comprises a groove formed therein.
Claim 5
Dependent Claim
22 words
The transistor of claim 1, wherein said source and drain areas are defined in a polysilicon layer deposited over said gate dielectric.
Claim 6
Dependent Claim
15 words
The transistor of claim 1, wherein said conductive region is formed in a semiconductor substrate.
Claim 7
Dependent Claim
16 words
The transistor of claim 5, wherein said conductive region comprises a doped region in said substrate.
Claim 8
Dependent Claim
134 words
A transistor fabricated on a substrate assembly having a conductive region formed therein, comprising: a generally insulating material having an opening therein defined in part by a sidewall, said opening extending from a top surface to said conductive region in said substrate assembly; a conductive silicon material within said opening, said conductive silicon material in physical contact with said sidewall of said insulating material and in electrical contact with said conductive region; a gate dielectric overlying said conductive silicon material; at least two semiconductor regions defining source and drain areas overlying said gate dielectric, said source and drain areas in operative relation to said conductive silicon material to form said transistor; and a conductive layer formed on said substrate, said conductive layer extending into electrical contact with said conductive silicon material within said opening.
Claim 9
Dependent Claim
134 words
A transistor fabricated on a substrate assembly having a conductive region formed therein, comprising: a generally insulating material having an opening therein defined in part by a sidewall, said opening extending from a top surface to said conductive region in said substrate assembly; a conductive silicon material within said opening, said conductive silicon material in physical contact with said sidewall of said insulating material and in electrical contact with said conductive region; a gate dielectric overlying said conductive silicon material; at least two semiconductor regions defining source and drain areas overlying said gate dielectric, said source and drain areas in operative relation to said conductive silicon material to form said transistor; and a conductive layer formed on said substrate, said conductive layer extending into electrical contact with said conductive silicon material within said opening.
Claim 10
Dependent Claim
14 words
The transistor of claim 7, wherein said conductive silicon material comprises conductively doped polysilicon.
Claim 11
Dependent Claim
18 words
The transistor of claim 7, wherein said opening in said generally insulating material comprises a groove formed therein.
Claim 12
Dependent Claim
22 words
The transistor of claim 7, wherein said source and drain areas are defined in a polysilicon layer deposited over said gate dielectric.
Claim 13
Dependent Claim
15 words
The transistor of claim 7, wherein said conductive region is formed in a semiconductor substrate.
Claim 14
Dependent Claim
16 words
The transistor of claim 11, wherein said conductive region comprises a doped region in said substrate.
Claim 15
Dependent Claim
124 words
A thin film transistor (TFT) fabricated on a starting substrate, said TFT comprising: a planarized insulating layer overlying said starting substrate; at least a single groove with continuous sidewalls having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive material; a conductively doped semiconductive material residing inside said groove, the material's surface being on essentially the same level as said planarized insulating layer's surface, said semiconductive material's surface forming said TFT gate; a TFT gate dielectric overlying said TFT gate; and a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region.
Claim 16
Dependent Claim
124 words
A thin film transistor (TFT) fabricated on a starting substrate, said TFT comprising: a planarized insulating layer overlying said starting substrate; at least a single groove with continuous sidewalls having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive material; a conductively doped semiconductive material residing inside said groove, the material's surface being on essentially the same level as said planarized insulating layer's surface, said semiconductive material's surface forming said TFT gate; a TFT gate dielectric overlying said TFT gate; and a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region.
Claim 17
Dependent Claim
17 words
The thin film transistor of claim 13, wherein said conductively doped semiconductive material comprises conductively doped polysilicon.
Claim 18
Dependent Claim
15 words
The thin film transistor of claim 13, wherein said semiconductive layer comprises conductively doped polysilicon.
Claim 19
Dependent Claim
22 words
The thin film transistor of claim 13, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying nitride layer.
Claim 20
Dependent Claim
23 words
The thin film transistor of claim 13, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying undoped oxide layer.
Claim 21
Dependent Claim
143 words
A thin film transistor fabricated on a starting substrate, said thin film transistor comprising: a planarized insulating layer overlying said starting substrate; at least a single groove with continuous vertical sidewalls having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive material; a conductively doped semiconductive material residing inside said groove, the material's upper surface being on essentially the same level as said planarized insulating layer's surface, said semiconductive material's upper surface forming said TFT gate and the semiconductive material's lower surface making contact to a diffusion region and a conductive interconnect; a TFT gate dielectric overlying said TFT gate; a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region.
Claim 22
Dependent Claim
143 words
A thin film transistor fabricated on a starting substrate, said thin film transistor comprising: a planarized insulating layer overlying said starting substrate; at least a single groove with continuous vertical sidewalls having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive material; a conductively doped semiconductive material residing inside said groove, the material's upper surface being on essentially the same level as said planarized insulating layer's surface, said semiconductive material's upper surface forming said TFT gate and the semiconductive material's lower surface making contact to a diffusion region and a conductive interconnect; a TFT gate dielectric overlying said TFT gate; a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region.
Claim 23
Dependent Claim
17 words
The thin film transistor of claim 18, wherein said conductively doped semiconductive material comprises conductively doped polysilicon.
Claim 24
Dependent Claim
15 words
The thin film transistor of claim 18, wherein said semiconductive layer comprises conductively doped polysilicon.
Claim 25
Dependent Claim
22 words
The thin film transistor of claim 18, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying nitride layer.
Claim 26
Dependent Claim
23 words
The thin film transistor of claim 18, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying undoped oxide layer.
Claim 27
Dependent Claim
176 words
A thin film transistor fabricated on a starting substrate, said thin film transistor comprising: a planarized insulating layer overlying said starting substrate, said planarized insulating layer having first and second grooves therein; at least a single groove with continuous essentially vertical sidewalls and having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive terminal; a conductively doped semiconductive material residing inside said groove, the material's upper surface being on essentially the same level as said planarized insulating layer's surface, said semiconductive material's upper surface forming said TFT gate and the semiconductive material's lower surface making contact to a diffusion region and a conductive interconnect; a TFT gate dielectric overlying said TFT gate; a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region; one of said source/drain terminals extending to and filling said second groove, thereby making contact to a second underlying conductive terminal.
Claim 28
Dependent Claim
176 words
A thin film transistor fabricated on a starting substrate, said thin film transistor comprising: a planarized insulating layer overlying said starting substrate, said planarized insulating layer having first and second grooves therein; at least a single groove with continuous essentially vertical sidewalls and having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive terminal; a conductively doped semiconductive material residing inside said groove, the material's upper surface being on essentially the same level as said planarized insulating layer's surface, said semiconductive material's upper surface forming said TFT gate and the semiconductive material's lower surface making contact to a diffusion region and a conductive interconnect; a TFT gate dielectric overlying said TFT gate; a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region; one of said source/drain terminals extending to and filling said second groove, thereby making contact to a second underlying conductive terminal.
Claim 29
Dependent Claim
17 words
The thin film transistor of claim 23, wherein said conductively doped semiconductive material comprises conductively doped polysilicon.
Claim 30
Dependent Claim
15 words
The thin film transistor of claim 23, wherein said semiconductive layer comprises conductively doped polysilicon.
Claim 31
Dependent Claim
22 words
The thin film transistor of claim 23, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying nitride layer.
Claim 32
Dependent Claim
23 words
The thin film transistor of claim 23, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying undoped oxide layer.
Claim 33
Dependent Claim
19 words
The thin film transistor of claim 23, wherein said one of said source/drain terminals conformally fills said second groove.
Claim 34
Dependent Claim
178 words
A thin film transistor (TFT) fabricated on a starting substrate, said thin film transistor comprising: a planarized insulating layer overlying said starting substrate, said planarized insulating layer having first and second grooves therein; said first and second grooves having continuous essentially vertical sidewalls and having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive terminal; a conductively doped semiconductive material residing inside said first and second grooves, the material's upper surface being on essentially the same level as said planarized insulating layer's surface, the semiconductive material's upper surface residing in said first groove forming said TFT gate with the semiconductive material's lower surface making contact to said underlying electrically conductive terminal; a TFT gate dielectric overlying said TFT gate; a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region; one of said source/drain terminals electrically coupling to said semiconductive material residing in said second groove.
Claim 35
Dependent Claim
178 words
A thin film transistor (TFT) fabricated on a starting substrate, said thin film transistor comprising: a planarized insulating layer overlying said starting substrate, said planarized insulating layer having first and second grooves therein; said first and second grooves having continuous essentially vertical sidewalls and having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive terminal; a conductively doped semiconductive material residing inside said first and second grooves, the material's upper surface being on essentially the same level as said planarized insulating layer's surface, the semiconductive material's upper surface residing in said first groove forming said TFT gate with the semiconductive material's lower surface making contact to said underlying electrically conductive terminal; a TFT gate dielectric overlying said TFT gate; a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region; one of said source/drain terminals electrically coupling to said semiconductive material residing in said second groove.
Claim 36
Dependent Claim
17 words
The thin film transistor of claim 29, wherein said conductively doped semiconductive material comprises conductively doped polysilicon.
Claim 37
Dependent Claim
15 words
The thin film transistor of claim 29, wherein said semiconductive layer comprises conductively doped polysilicon.
Claim 38
Dependent Claim
18 words
The thin film transistor of claim 29, wherein said planarized insulating layer comprises a layer of planarized oxide.
Claim 39
Dependent Claim
21 words
The thin film transistor of claim 29, wherein said planarized insulating layer comprises a BPSG layer overlaid with a nitride layer.
Claim 40
Dependent Claim
23 words
The thin film transistor of claim 29, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying undoped oxide layer.
Claim 41
Dependent Claim
34 words
The thin film transistor of claim 29, wherein said underlying electrically conductive terminal comprises at least one material selected from the group consisting of a conductively doped polysilicon and a conductively doped diffusion area.
Claim 42
Dependent Claim
104 words
An inverter fabricated on a starting substrate, said inverter comprising: a pulldown transistor, said pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer over said pulldown transistor; a first planarized conductive polysilicon plug forming a thin film transistor gate connecting to a coupling node and a second planarized conductive polysilicon plug providing connection to said control gate of said pulldown transistor; a gate dielectric overlying said first planarized conductive polysilicon plugs; a patterned polysilicon layer doped such that a channel region aligns to said thin film transistor gate and a source/drain region aligns to each side of said channel region.
Claim 43
Dependent Claim
104 words
An inverter fabricated on a starting substrate, said inverter comprising: a pulldown transistor, said pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer over said pulldown transistor; a first planarized conductive polysilicon plug forming a thin film transistor gate connecting to a coupling node and a second planarized conductive polysilicon plug providing connection to said control gate of said pulldown transistor; a gate dielectric overlying said first planarized conductive polysilicon plugs; a patterned polysilicon layer doped such that a channel region aligns to said thin film transistor gate and a source/drain region aligns to each side of said channel region.
Claim 44
Dependent Claim
49 words
The inverter of claim 36, wherein the connection between said first planarized conductive polysilicon plug and said coupling node and the connection between said second planarized conductive polysilicon plug and said control gate of said pulldown transistor are formed in a both a substantially vertical and substantially horizontal fashion.
Claim 45
Dependent Claim
45 words
The inverter of claim 36, wherein the connection between said first planarized conductive polysilicon plug and said coupling and the connection between said second planarized conductive polysilicon plug and said control gate of said pulldown transistor are formed in a only a substantially horizontal fashion.
Claim 46
Dependent Claim
26 words
A planarized cross-coupled latch fabricated on a starting substrate, comprising a first planarized inverter of claim 36 cross-coupled to a second planarized inverter of claim 36.
Claim 47
Dependent Claim
24 words
The planarized cross-coupled latch of claim 39, wherein said cross-coupled latch functions as a cross-coupled static storage cell in a static random access memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-31 | 2000-09-30 | 2001-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-31 | 2004-09-30 | 2005-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-31 | 2008-09-30 | 2009-04-01 | $7700.00 | Window Closed / Lapsed |