Electrically programmable read-only memory cell

Claim 2

An electrically programmable read-only memory cell comprising: a substrate having a first conductivity type and a primary surface; a first doped region having a second conductivity type that is opposite the first conductivity type, wherein the first doped region lies adjacent to the primary surface of the substrate; a pillar including a semiconductor material and overlying the first doped region and extending therefrom, wherein the pillar includes: a central region having the first conductivity type, wherein all of the central region overlies the first doped region; and a second doped region lying on the central region, wherein the second doped region has the second conductivity type; a first dielectric layer lying adjacent to a side of the pillar; a spacer lying adjacent to the first dielectric layer, wherein the spacer acts as a floating gate; a second dielectric layer lying adjacent to the spacer, wherein the second dielectric layer includes an opening that overlies the second doped region; a conductive member that lies adjacent to the second dielectric layer; and an interconnect that is electrically connected to the second doped region.

Claim 3

The memory cell of claim 1, wherein the pillar includes single crystal silicon.

Claim 4

The memory cell of claim 1, wherein the central region acts as a channel region and the conductive member acts as a control gate.

Claim 5

The memory cell of claim 1, wherein the spacer has a resistivity no greater than 0.05 ohm·centimeter.

Claim 6

The memory cell of claim 1, wherein the conductive member includes an opening that overlies the second doped region.

Claim 7

The memory cell of claim 1, wherein: a region of the pillar has a graded doping concentration; and the region is selected from a group consisting of the second doped region and the central region.

Claim 8

A memory array that includes a first plurality of electrically programmable read-only memory cells comprising: a substrate having a first conductivity type and a primary surface; at least one first doped region having a second conductivity type that is opposite the first conductivity type, wherein the at least one first doped region lies adjacent to the primary surface of the substrate; pillars including a semiconductor material, wherein: all of each pillar overlies one of the at least one first doped region; the pillars include central regions having the first conductivity type; and the pillars include second doped regions lying on the central regions, wherein the second doped regions have the second conductivity type; a first dielectric layer lying adjacent to sides of the pillars; spacers lying adjacent to the first dielectric layer, wherein the spacers act as floating gates; a second dielectric layer lying adjacent to the spacers; conductive members lying adjacent to the second dielectric layer; and interconnects that are electrically connected to the second doped regions, wherein lengths of the conductive members are perpendicular to lengths of the interconnects.

Claim 9

A memory array that includes a first plurality of electrically programmable read-only memory cells comprising: a substrate having a first conductivity type and a primary surface; at least one first doped region having a second conductivity type that is opposite the first conductivity type, wherein the at least one first doped region lies adjacent to the primary surface of the substrate; pillars including a semiconductor material, wherein: all of each pillar overlies one of the at least one first doped region; the pillars include central regions having the first conductivity type; and the pillars include second doped regions lying on the central regions, wherein the second doped regions have the second conductivity type; a first dielectric layer lying adjacent to sides of the pillars; spacers lying adjacent to the first dielectric layer, wherein the spacers act as floating gates; a second dielectric layer lying adjacent to the spacers; conductive members lying adjacent to the second dielectric layer; and interconnects that are electrically connected to the second doped regions, wherein lengths of the conductive members are perpendicular to lengths of the interconnects.

Claim 10

The memory array of claim 7, wherein a second plurality of memory cells of the first plurality of memory cells may be erased simultaneously.

Claim 11

The memory array of claim 7, wherein each of the pillars includes single crystal silicon.

Claim 12

The memory array of claim 7, wherein each of the central regions acts as a channel region and each of the conductive members acts as control gates.

Claim 13

The memory array of claim 7, wherein the second dielectric layer includes openings that overlie the second doped regions.

Claim 14

The memory array of claim 7, wherein the conductive members include openings that overlie the second doped regions.

Claim 15

The memory array of claim 7, wherein: regions of the pillars have graded doping concentrations; and the regions are selected from a group consisting of the second doped regions and the central regions.

Claim 16

The memory array of claim 7, wherein the at least one first doped region is a plurality of doped strips lying within the substrate, wherein field isolation regions lie between the doped strips.

Claim 17

The memory array of claim 7, wherein: the at least one first doped region is electrically connected to the pillars of a second plurality of memory cells and the first doped region acts as a common source region for the second plurality of memory cells; one of the conductive members acts as gate electrodes for a third plurality of memory cells and as a word line for the memory array; one of the interconnects is electrically connected to the second doped regions of a fourth plurality of memory cells and acts as a bit line for the memory array; the second plurality of memory cells includes at least a portion of the first plurality of memory cells; and only one memory cell is common to the third and fourth pluralities of memory cells.

Claim 18

An electrically programmable read-only memory cell comprising: a substrate having a first conductivity type and a primary surface; a first doped region having a second conductivity type that is opposite the first conductivity type, wherein the first doped region lies adjacent to the primary surface of the substrate; a pillar including a semiconductor material and overlying the first doped region and extending therefrom, wherein the pillar includes: a central region having the first conductivity type, wherein all of the central region overlies the first doped region; and a second doped region overlying on the central region, wherein the second doped region has the second conductivity type; a first dielectric layer lying adjacent to a side of the pillar; a spacer lying adjacent to the first dielectric layer and laterally surrounding the central region, wherein the spacer acts as a floating gate; a second dielectric layer lying adjacent to the spacer; a conductive member that lies adjacent to the second dielectric layer; and an interconnect that is electrically connected to the second doped region.

Claim 19

An electrically programmable read-only memory cell comprising: a substrate having a first conductivity type and a primary surface; a first doped region having a second conductivity type that is opposite the first conductivity type, wherein the first doped region lies adjacent to the primary surface of the substrate; a pillar including a semiconductor material and overlying the first doped region and extending therefrom, wherein the pillar includes: a central region having the first conductivity type, wherein all of the central region overlies the first doped region; and a second doped region overlying on the central region, wherein the second doped region has the second conductivity type; a first dielectric layer lying adjacent to a side of the pillar; a spacer lying adjacent to the first dielectric layer and laterally surrounding the central region, wherein the spacer acts as a floating gate; a second dielectric layer lying adjacent to the spacer; a conductive member that lies adjacent to the second dielectric layer; and an interconnect that is electrically connected to the second doped region.

Claim 20

The memory cell of claim 16, wherein the pillar includes single crystal silicon.

Claim 21

The memory cell of claim 16, wherein the central region acts as a channel region and the conductive member acts as a control gate.

Claim 22

The memory cell of claim 16, wherein the second dielectric layer includes an opening that overlies the second doped region.

Claim 23

The memory cell of claim 16, wherein the conductive member includes an opening that overlies the second doped region.

Claim 24

The memory cell of claim 16, wherein: a region of the pillar has a graded doping concentration; and the region is selected from a group consisting of the second doped region and the central region.

Claim 25

A memory array that includes a first plurality of electrically programmable read-only memory cells comprising: a substrate having a first conductivity type and a primary surface; at least one first doped region having a second conductivity type that is opposite the first conductivity type, wherein the at least one first doped region lies adjacent to the primary surface of the substrate; pillars including a semiconductor material, wherein: all of each pillar overlies one of the at least one first doped region; the pillars include second doped regions overlying the at least one first doped region, wherein: the second doped regions have the second conductivity type; and the at least one first doped region is electrically connected to the second doped regions of a second plurality of memory cells; the second plurality of memory cells includes at least a portion of the first plurality of memory cells; and a combination of the first and second doped regions acts as a common source region for the second plurality of memory cells; the pillars include central regions lying only on the second doped regions, wherein the central regions have the first conductivity type; and the pillars include third doped regions lying on the central regions, wherein the third doped regions have the second conductivity type; a first dielectric layer lying adjacent to sides of the pillars; spacers lying adjacent to the first dielectric layer, wherein the spacers act as floating gates; a second dielectric layer lying adjacent to the spacers; conductive members lying adjacent to the second dielectric layer, wherein one of the conductive members acts as gate electrodes for a third plurality of memory cells and as a word line for the memory array; and interconnects that are electrically connected to the third doped regions, wherein: one of the interconnects is electrically connected to the third doped regions of a fourth plurality of memory cells and acts as a bit line for the memory array; and only one memory cell is common to the third and fourth pluralities of memory cells.

Claim 26

A memory array that includes a first plurality of electrically programmable read-only memory cells comprising: a substrate having a first conductivity type and a primary surface; at least one first doped region having a second conductivity type that is opposite the first conductivity type, wherein the at least one first doped region lies adjacent to the primary surface of the substrate; pillars including a semiconductor material, wherein: all of each pillar overlies one of the at least one first doped region; the pillars include second doped regions overlying the at least one first doped region, wherein: the second doped regions have the second conductivity type; and the at least one first doped region is electrically connected to the second doped regions of a second plurality of memory cells; the second plurality of memory cells includes at least a portion of the first plurality of memory cells; and a combination of the first and second doped regions acts as a common source region for the second plurality of memory cells; the pillars include central regions lying only on the second doped regions, wherein the central regions have the first conductivity type; and the pillars include third doped regions lying on the central regions, wherein the third doped regions have the second conductivity type; a first dielectric layer lying adjacent to sides of the pillars; spacers lying adjacent to the first dielectric layer, wherein the spacers act as floating gates; a second dielectric layer lying adjacent to the spacers; conductive members lying adjacent to the second dielectric layer, wherein one of the conductive members acts as gate electrodes for a third plurality of memory cells and as a word line for the memory array; and interconnects that are electrically connected to the third doped regions, wherein: one of the interconnects is electrically connected to the third doped regions of a fourth plurality of memory cells and acts as a bit line for the memory array; and only one memory cell is common to the third and fourth pluralities of memory cells.