US5350937A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory device having a floating gate
Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1992-10-07
•
Granted: 1994-09-27
•
Expires: 2012-10-07
Abstract
Abstract A MOS type semiconductor device comprising a protruded part provided on a semiconductor substrate, a semiconductor film formed on the side surface thereof, which is defined as a floating gate, and a gate electrode covered with the semiconductor film. In particular, a MOS memory device manufactured by providing a number of the above-mentioned semiconductor devices, by forming an impurity region on top of the protruded part of each semiconductor device, by forming a contact on the impurity region, and by providing a wiring that crosses a gate wiring.
Inventors
- 👤 Shunpei Yamazaki
- 👤 Yasuhiko Takemura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:28
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10B; H10B69/00; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
269 words
A semiconductor device having a source, drain, gate electrode, and a floating gate electrode comprising: a semiconductor substrate having a lower surface and a protrusion extending from the lower surface, said protrusion having a side surface and being added with an impurity in an upper portion thereof so that said source of drain is formed in said upper portion of the protrusion; said floating gate electrode formed adjacent to said side surface of the protrusion with a first insulating layer therebetween; said gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; an interlayer insulator formed on said semiconductor substrate, said floating gate electrode and said gate electrode with a contact hole opened through said insulator on the upper portion of said protrusion where the thickness of the interlayer insulator over the lower surface of the semiconductor substrate is greater than the thickness thereof over the protrusion; an impurity region formed within said lower surface of the semiconductor substrate to provide the other of said source or drain, said region being located such that said gate electrode extends between said impurity region and said upper portion of the protrusion whereby said source, drain, floating gate electrode, and gate electrode function as a storage device and said source, drain and gate electrode function as a select device to sense the state of the storage device; a first wiring extending in a first direction and connected to said upper portion of said protrusion through said contact hole; and said impurity region formed within the semiconductor substrate extending in a second direction orthogonal to the first direction.
Claim 2
Dependent Claim
269 words
A semiconductor device having a source, drain, gate electrode, and a floating gate electrode comprising: a semiconductor substrate having a lower surface and a protrusion extending from the lower surface, said protrusion having a side surface and being added with an impurity in an upper portion thereof so that said source of drain is formed in said upper portion of the protrusion; said floating gate electrode formed adjacent to said side surface of the protrusion with a first insulating layer therebetween; said gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; an interlayer insulator formed on said semiconductor substrate, said floating gate electrode and said gate electrode with a contact hole opened through said insulator on the upper portion of said protrusion where the thickness of the interlayer insulator over the lower surface of the semiconductor substrate is greater than the thickness thereof over the protrusion; an impurity region formed within said lower surface of the semiconductor substrate to provide the other of said source or drain, said region being located such that said gate electrode extends between said impurity region and said upper portion of the protrusion whereby said source, drain, floating gate electrode, and gate electrode function as a storage device and said source, drain and gate electrode function as a select device to sense the state of the storage device; a first wiring extending in a first direction and connected to said upper portion of said protrusion through said contact hole; and said impurity region formed within the semiconductor substrate extending in a second direction orthogonal to the first direction.
Claim 3
Dependent Claim
22 words
The semiconductor device of claim 1 wherein said gate electrode is selected from a group consisting of doped semiconductor, metal and silicide.
Claim 4
Dependent Claim
22 words
The semiconductor device of claim 1 wherein said semiconductor film is encapsulated with said first insulating layer and said second insulating layer.
Claim 5
Dependent Claim
24 words
The semiconductor device of claim 1 wherein said side surface of the protrusion is approximately vertical to the major surface of said semiconductor substrate.
Claim 6
Dependent Claim
250 words
A semiconductor device comprising: a semiconductor substrate having a plurality of protrusions arranged in a row and column form, each of said protrusions having a side surface and being added with an impurity in an upper portion thereof to provide a source of drain; a plurality of semiconductor elements associated with said protrusions, respectively where each of said semiconductor elements comprises: a semiconductor film comprising a floating gate electrode and formed adjacent to said side surface of the protrusion with a first insulating layer therebetween; a gate electrode formed adjacent to said semiconductor film with a second insulating layer therebetween; and an impurity region formed within said semiconductor substrate to provide the other of said source or drain, said region located such that semiconductor film extends between said impurity region and said upper portion of the protrusion whereby said source, drain, floating gate electrode, and gate electrode function as a storage device and said source, drain and gate electrode function as a select device to sense the state of the storage device, a plurality of row lines connected with the gate electrodes of the corresponding semiconductor elements arranged along said row lines; a plurality of first lines connected with the upper portions of the corresponding protrusions arranged along said row or column lines; and a plurality of second lines connected with the impurity regions in the semiconductor substrate, the second lines arranged in the direction of the other of said row and column lines along which the first lines extend.
Claim 7
Dependent Claim
250 words
A semiconductor device comprising: a semiconductor substrate having a plurality of protrusions arranged in a row and column form, each of said protrusions having a side surface and being added with an impurity in an upper portion thereof to provide a source of drain; a plurality of semiconductor elements associated with said protrusions, respectively where each of said semiconductor elements comprises: a semiconductor film comprising a floating gate electrode and formed adjacent to said side surface of the protrusion with a first insulating layer therebetween; a gate electrode formed adjacent to said semiconductor film with a second insulating layer therebetween; and an impurity region formed within said semiconductor substrate to provide the other of said source or drain, said region located such that semiconductor film extends between said impurity region and said upper portion of the protrusion whereby said source, drain, floating gate electrode, and gate electrode function as a storage device and said source, drain and gate electrode function as a select device to sense the state of the storage device, a plurality of row lines connected with the gate electrodes of the corresponding semiconductor elements arranged along said row lines; a plurality of first lines connected with the upper portions of the corresponding protrusions arranged along said row or column lines; and a plurality of second lines connected with the impurity regions in the semiconductor substrate, the second lines arranged in the direction of the other of said row and column lines along which the first lines extend.
Claim 8
Dependent Claim
22 words
The semiconductor device of claim 5 wherein said gate electrodes are selected from the group consisting of doped semiconductor, metal and silicide.
Claim 9
Dependent Claim
22 words
The semiconductor device of claim 5 wherein said semiconductor film is encapsulated with said first insulating layer and said second insulating layer.
Claim 10
Dependent Claim
24 words
The semiconductor device of claim 5 wherein said side surface of the protrusions are approximately vertical to a major surface of said semiconductor substrate.
Claim 11
Dependent Claim
30 words
The device of claim 1 further comprising a wiring formed on said interlayer insulator wherein said wiring electrically contacts with said upper portion of the protrusion through said contact hole.
Claim 12
Dependent Claim
41 words
The device of claim 5 further comprising an interlayer insulator covering said semiconductor substrate having said plurality of semiconductor elements, wherein said plurality of column lines contact the upper portion of the protrusions through contact holes opened through said interlayer insulator.
Claim 13
Dependent Claim
198 words
A semiconductor device comprising: a semiconductor substrate having a plurality of protrusions arranged in a matrix, each of said protrusion having an upper portion and a side surface; non-volatile memory devices associated with said protrusions, wherein each of said memory device comprises: source or drain region formed in the upper portion of said protrusion; the other of the source or drain regions formed in a surface portion of said semiconductor substrate adjacent to said protrusion; a floating gate formed adjacent to the side surface of said protrusion with a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate with a second insulating film therebetween, a plurality of first wirings extending on and electrically contacting with the upper portions of said protrusions, each said first wiring extending in one of a row direction and column direction of said matrix, said other of the source and drain regions extending in the other of said row and column directions along which the first wirings extend, wherein an interlayer is provided between said wiring and said semiconductor substrate and wherein said wiring contacts said upper portions of the protrusions through contact holes provided through said interlayer insulator.
Claim 14
Dependent Claim
198 words
A semiconductor device comprising: a semiconductor substrate having a plurality of protrusions arranged in a matrix, each of said protrusion having an upper portion and a side surface; non-volatile memory devices associated with said protrusions, wherein each of said memory device comprises: source or drain region formed in the upper portion of said protrusion; the other of the source or drain regions formed in a surface portion of said semiconductor substrate adjacent to said protrusion; a floating gate formed adjacent to the side surface of said protrusion with a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate with a second insulating film therebetween, a plurality of first wirings extending on and electrically contacting with the upper portions of said protrusions, each said first wiring extending in one of a row direction and column direction of said matrix, said other of the source and drain regions extending in the other of said row and column directions along which the first wirings extend, wherein an interlayer is provided between said wiring and said semiconductor substrate and wherein said wiring contacts said upper portions of the protrusions through contact holes provided through said interlayer insulator.
Claim 15
Dependent Claim
176 words
A semiconductor device comprising: a semiconductor substrate having a plurality of protrusions in the form of a matrix, each of said protrusion having an upper portion and a side surface; non-volatile memory devices associated with said protrusions, wherein each of said memory device comprises: a first impurity region formed in the upper portion of said protrusion; a second impurity region formed in a surface portion of said semiconductor substrate adjacent to said protrusion; a floating gate formed adjacent to the side surface of said protrusion with a first insulating layer therebetween; and as gate electrode formed adjacent to said floating gate with a second insulating film therebetween, a plurality of first lines connected with the first impurity regions arranged in one of a column and row direction of said matrix; a plurality of second lines connected with the second impurity regions arranged in the other of said row and column directions along which the first lines extend; a plurality of gate lines connected with the gate electrodes arranged in one of said column and row directions.
Claim 16
Dependent Claim
176 words
A semiconductor device comprising: a semiconductor substrate having a plurality of protrusions in the form of a matrix, each of said protrusion having an upper portion and a side surface; non-volatile memory devices associated with said protrusions, wherein each of said memory device comprises: a first impurity region formed in the upper portion of said protrusion; a second impurity region formed in a surface portion of said semiconductor substrate adjacent to said protrusion; a floating gate formed adjacent to the side surface of said protrusion with a first insulating layer therebetween; and as gate electrode formed adjacent to said floating gate with a second insulating film therebetween, a plurality of first lines connected with the first impurity regions arranged in one of a column and row direction of said matrix; a plurality of second lines connected with the second impurity regions arranged in the other of said row and column directions along which the first lines extend; a plurality of gate lines connected with the gate electrodes arranged in one of said column and row directions.
References Cited (Backward Citations)
US5017977A
Cited
JPS61256673A
Cited
US4774556A
Cited
JPS6276563A
Cited
US4929988A
Cited
JPH01291470A
Cited
US5053842A
Cited
US5071782A
Cited
US5078498A
Cited
US5146426A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-26 | 1998-03-28 | 1998-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-26 | 2002-03-28 | 2002-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-26 | 2006-03-28 | 2006-09-27 | $7700.00 | Window Closed / Lapsed |