US4530149A
Expired / Lapsed
US
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Method for fabricating a self-aligned vertical IGFET
Assignee: RCA Corp
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Filing: 1985-04-28
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Granted: 1985-07-23
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Expires: 2005-04-28
Abstract
Abstract A vertical IGFET device is formed on a substrate which includes a monocrystalline silicon portion at a surface thereof. An apertured insulated gate electrode is disposed on the substrate surface such that an area of monocrystalline silicon is exposed through the aperture. An epitaxial silicon region extends from the substrate surface within the gate electrode aperture and is appropriately doped such that a predetermined voltage applied to the insulated gate electrode forms a channel region in the epitaxial region adjacent thereto. The vertical IGFET is fabricated by a self-aligned technique, wherein the insulated gate electrode includes a first, underlying insulating layer and a second, overlying insulating layer. The second insulating layer protects the gate electrode when the first insulating layer is defined.
Inventors
- 👤 Lubomir L. Jastrzebski
- 👤 Alfred C. Ipri
- 👤 Achilles G. Kokkas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10B; H10B10/00; H10B10/12; H10D30/01; H10D30/021; H10D30/025; H10D64/00; H10D64/01; H10D64/011; H10D88/00; H10P; H10P14/00; H10P14/20; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
169 words
A method for fabricating a vertical IGFET device, comprising the steps of: (a) providing a substrate having a monocrystalline silicon drain portion of first conductivity type at a surface thereof; (b) forming a first insulating layer on said surface; (c) forming a gate electrode of predetermined thickness on the first insulating layer, the electrode having an aperture therethrough, said aperture overlying a portion of said monocrystalline silicon portion; (d) coating the apertured electrode with a second insulating layer so as to form an insulated gate; (e) etching the first insulating layer, using the insulated gate as an etch mask, so as to expose an area of monocrystalline silicon within the aperture of the insulated gate; (f) epitaxially growing silicon from said area of monocrystalline silicon so as to substantially fill the aperture; and (g) doping said epitaxial silicon so as to form a body region of second conductivity type in opposition to said gate electrode, and a source region of first conductivity type overlying said second conductivity type portion.
Claim 2
Independent Claim
169 words
A method for fabricating a vertical IGFET device, comprising the steps of: (a) providing a substrate having a monocrystalline silicon drain portion of first conductivity type at a surface thereof; (b) forming a first insulating layer on said surface; (c) forming a gate electrode of predetermined thickness on the first insulating layer, the electrode having an aperture therethrough, said aperture overlying a portion of said monocrystalline silicon portion; (d) coating the apertured electrode with a second insulating layer so as to form an insulated gate; (e) etching the first insulating layer, using the insulated gate as an etch mask, so as to expose an area of monocrystalline silicon within the aperture of the insulated gate; (f) epitaxially growing silicon from said area of monocrystalline silicon so as to substantially fill the aperture; and (g) doping said epitaxial silicon so as to form a body region of second conductivity type in opposition to said gate electrode, and a source region of first conductivity type overlying said second conductivity type portion.
Claim 3
Dependent Claim
14 words
A method in accordance with claim 1, wherein said substrate is monocrystal line silicon.
Claim 4
Dependent Claim
24 words
A method in accordance with claim 1, wherein said first insulating layer is selected from the group consisting of silicon nitride and silicon dioxide.
Claim 5
Dependent Claim
30 words
A method in accordance with claim 1, wherein said first insulating layer comprises: a lower layer disposed on said substrate surface; and an upper layer disposed on said lower layer.
Claim 6
Dependent Claim
14 words
A method in accordance with claim 4, wherein said lower layer is silicon dioxide.
Claim 7
Dependent Claim
14 words
A method in accordance with claim 5, wherein said upper layer is silicon nitride.
Claim 8
Dependent Claim
15 words
A method in accordance with claim 1, wherein said gate electrode comprises doped, polycrystalline silicon.
Claim 9
Dependent Claim
29 words
A method in accordance with claim 7, wherein said gate electrode is formed by the steps of: forming a layer of doped polycrystalline silicon; and photolithographically defining said aperture.
Claim 10
Dependent Claim
50 words
A method in accordance with claim 7, wherein said gate electrode is formed by the steps of: forming a layer of doped polycrystalline silicon; forming a supplementary insulating layer on the surface of said polycrystalline silicon; and forming an aperture through said supplementary insulating layer and said polycrystalline silicon layer.
Claim 11
Dependent Claim
15 words
A method in accordance with claim 1, wherein said second insulating layer is silicon dioxide.
Claim 12
Dependent Claim
43 words
A method in accordance with claim 10, further comprising: providing a doped polycrystalline silicon gate electrode; and forming said second insulating layer by thermal oxidation so as to yield a predetermined thickness of said second insulating layer within said aperture in said electrode.
Claim 13
Dependent Claim
24 words
A method in accordance with claim 1, further comprising: between steps (e) and (f), doping said area of monocrystalline silicon exposed within said aperture.
Claim 14
Dependent Claim
23 words
A method in accordance with claim 12, comprising ion implanting a conductivity modifier of first conductivity type so as to achieve said doping.
Claim 15
Dependent Claim
18 words
A method in accordance with claim 1, further comprising doping said epitaxial silicon simultaneous with the growing thereof.
Claim 16
Dependent Claim
33 words
A method in accordance with claim 1, wherein said substrate comprises an insulating wafer having a layer disposed on a surface thereof, said layer comprising a monocrystalline silicon island surrounded by silicon dioxide.
Claim 17
Dependent Claim
44 words
A method in accordance with claim 15, wherein said substrate is formed by the steps of: forming a monocrystalline silicon layer on an insulating wafer; masking a portion of said silicon layer; oxidizing the unmasked portion of said silicon layer; and stripping said mask.
Claim 18
Independent Claim
169 words
A method for fabricating a vertical IGFET device, comprising the steps of: (a) providing a substrate having a monocrystalline silicon source portion of first conductivity type at a surface thereof; (b) forming a first insulating layer on said surface; (c) forming a gate electrode of predetermined thickness on the first insulating layer, the electrode having an aperture therethrough, said aperture overlying a portion of said monocrystalline silicon portion; (d) coating the apertured electrode with a second insulating layer so as to form an insulated gate; (e) etching the first insulating layer, using the insulated gate as an etch mask, so as to expose an area of monocrystalline silicon within the aperture of the insulated gate; (f) epitaxially growing silicon from said area of monocrystalline silicon so as to substantially fill the aperture; and (g) doping said epitaxial silicon so as to form a body region of second conductivity type in opposition to said gate electrode, and a drain region of first conductivity type overlying said second conductivity type portion.
Claim 19
Independent Claim
169 words
A method for fabricating a vertical IGFET device, comprising the steps of: (a) providing a substrate having a monocrystalline silicon source portion of first conductivity type at a surface thereof; (b) forming a first insulating layer on said surface; (c) forming a gate electrode of predetermined thickness on the first insulating layer, the electrode having an aperture therethrough, said aperture overlying a portion of said monocrystalline silicon portion; (d) coating the apertured electrode with a second insulating layer so as to form an insulated gate; (e) etching the first insulating layer, using the insulated gate as an etch mask, so as to expose an area of monocrystalline silicon within the aperture of the insulated gate; (f) epitaxially growing silicon from said area of monocrystalline silicon so as to substantially fill the aperture; and (g) doping said epitaxial silicon so as to form a body region of second conductivity type in opposition to said gate electrode, and a drain region of first conductivity type overlying said second conductivity type portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-22 | 1989-01-21 | 1989-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-22 | 1993-01-21 | 1993-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-22 | 1997-01-21 | 1997-07-23 | $7700.00 | Window Closed / Lapsed |