US4287660A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods of manufacturing semiconductor devices
Assignee: US Philips Corp
•
Filing: 1978-11-24
•
Granted: 1981-09-08
•
Expires: 1998-11-24
Abstract
Abstract A method of manufacturing a semiconductor device is set forth in which a masking layer is formed on part of the surface of a deposited layer of a relatively high resistivity polycrystalline semiconductor material being present on an insulating layer provided at a surface of a semiconductor body or portion thereof. A relatively low resistivity conductive region having a substantially uniform narrow line width is defined in the polycrystalline layer by effecting a diffusion process to laterally diffuse a doping element into a portion of the polycrystalline layer underlying an edge portion of the masking layer without diffusing the doping element through the insulating layer into the semiconductor body or portion thereof.
Inventors
- 👤 Keith H. Nicholas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:01
CPC Classifications
H; H10; H10B; H10B10/00; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10P; H10P32/00; H10P32/30; H10P32/302; H10P50/00; H10P50/60; H10P50/66; H10P50/663; H10P50/667; H10P76/00; H10P76/40; H10W; H10W20/00; H10W20/20; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/924; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
181 words
A method of manufacturing a semiconductor device comprising a low resistivity conductive region having a substantially uniform narrow line width, said method comprising the steps of: (a) providing a semiconductor element having an insulating layer disposed at at least a surface part thereof, (b) depositing a layer of relatively high resistivity polycrystalline semiconductor material on said insulating layer, (c) forming a masking layer on a part of the exposed surface of said polycrystalline layer, (d) removing a part of said polycrystalline layer such that an edge thereof is exposed throughout the thickness thereof at an edge portion of said masking layer, (e) diffusing via the exposed edge portion a doping element laterally into a portion of said polycrystalline layer underlying said edge portion of said masking layer in the substantial absence of diffusing said doping element through said insulating layer itself into the semiconductor element, thereby forming said conductive region, (f) removing said masking layer, and (g) subjecting at least a part of the exposed polycrystalline layer adjacent said conductive region to an etching treatment to selectively remove undiffused portions thereof.
Claim 2
Independent Claim
181 words
A method of manufacturing a semiconductor device comprising a low resistivity conductive region having a substantially uniform narrow line width, said method comprising the steps of: (a) providing a semiconductor element having an insulating layer disposed at at least a surface part thereof, (b) depositing a layer of relatively high resistivity polycrystalline semiconductor material on said insulating layer, (c) forming a masking layer on a part of the exposed surface of said polycrystalline layer, (d) removing a part of said polycrystalline layer such that an edge thereof is exposed throughout the thickness thereof at an edge portion of said masking layer, (e) diffusing via the exposed edge portion a doping element laterally into a portion of said polycrystalline layer underlying said edge portion of said masking layer in the substantial absence of diffusing said doping element through said insulating layer itself into the semiconductor element, thereby forming said conductive region, (f) removing said masking layer, and (g) subjecting at least a part of the exposed polycrystalline layer adjacent said conductive region to an etching treatment to selectively remove undiffused portions thereof.
Claim 3
Dependent Claim
50 words
A method as claimed in claim 1, wherein subsequent to the diffusion process the masking layer is removed and the polycrystalline layer is subjected to an etching treatment to selectively remove the undiffused portions thereof to thereby leave at said edge of the polycrystalline layer said low resistivity conductive region.
Claim 4
Dependent Claim
40 words
A method as claimed in claim 1, wherein the device manufactured comprises at least one insulated gate field effect transistor and said conductive region of said polycrystalline semiconductor layer forms at least part of the gate electrode of said transistor.
Claim 5
Dependent Claim
84 words
A method as in claim 1, wherein said semiconductor device is an integrated circuit and at least one portion of said polycrystalline semiconductor layer constitutes a conductive track which crosses and is insulated from an underlying diffused connection region in said semiconductor body, the opposite edge portions of the track at the area of the crossing being converted into said low resistivity conductive regions by said lateral diffusion in the presence of a masking layer on the track at the area of the crossing.
Claim 6
Dependent Claim
63 words
A method as in claim 4, wherein said integrated circuit comprises a plurality of insulated gate field effect transistors having their gate electrodes formed by doped portions of said polycrystalline semiconductor layer, said diffusion also being carried out to form at least parts of the source and drain regions of transistors and to dope exposed upper surface portions of said polycrystalline semiconductor layer.
Claim 7
Dependent Claim
107 words
A method as in claim 4, wherein subsequent to forming said low resistivity diffused conductive regions at the opposite edge portions of the track at the area of the crossing, any remaining undiffused central portion of the track at the area of the crossing is selectively removed and a further diffusion is carried out to form at the area of the crossing a diffused surface region in the semiconductor body in the form of a strip situated intermediate the portions of the body above which said low resistivity diffused conductive regions of the track are present, said diffused surface region forming part of the diffused connection region.
Claim 8
Dependent Claim
64 words
A method as in claim 6, wherein the further diffusion step is also carried out to form at the area of the crossing diffused surface regions in the semiconductor body situated adjacent and extending inwardly below said opposite edges of the track at which said low resistivity diffused conductive regions have been formed, said diffused surface regions forming parts of the diffused connection region.
Claim 9
Independent Claim
173 words
A method of manufacturing a semiconductor device comprising a low resistivity conductive region with a substantially uniform narrow line width and comprising at least one insulated gate field effect transistor, said method comprising the steps of: (a) providing a semiconductor element having an insulating layer disposed at at least a surface part thereof, (b) depositing a layer of relatively high resistivity polycrystalline semiconductor material on said insulating layer, (c) forming a masking layer on a part of the exposed surface of said polycrystalline layer, (d) removing a part of said polycrystalline layer such that an edge thereof is exposed throughout the thickness thereof at an edge portion of said masking layer, (e) diffusing via said exposed edge portion a doping element laterally into a portion of said polycrystalline layer underlying said edge portion of said masking layer without diffusing said doping element through said insulating layer itself into said semiconductor element, thereby forming said conductive region, and (f) forming from said conductive region at least part of a gate electrode for said transistor.
Claim 10
Independent Claim
173 words
A method of manufacturing a semiconductor device comprising a low resistivity conductive region with a substantially uniform narrow line width and comprising at least one insulated gate field effect transistor, said method comprising the steps of: (a) providing a semiconductor element having an insulating layer disposed at at least a surface part thereof, (b) depositing a layer of relatively high resistivity polycrystalline semiconductor material on said insulating layer, (c) forming a masking layer on a part of the exposed surface of said polycrystalline layer, (d) removing a part of said polycrystalline layer such that an edge thereof is exposed throughout the thickness thereof at an edge portion of said masking layer, (e) diffusing via said exposed edge portion a doping element laterally into a portion of said polycrystalline layer underlying said edge portion of said masking layer without diffusing said doping element through said insulating layer itself into said semiconductor element, thereby forming said conductive region, and (f) forming from said conductive region at least part of a gate electrode for said transistor.
Claim 11
Dependent Claim
55 words
A method as in claim 8, wherein at least parts of the source and drain regions of said transistor are formed by introducing an impurity into said semiconductor body at opposite sides of said conductive regions, said conductive region masking against impurity introduction into the portion of the semiconductor body lying below said strip portion.
Claim 12
Dependent Claim
71 words
A method as in claim 9, wherein said semiconductor device is an integrated circuit comprising a plurality of insulated gate field effect transistors having their gate electrodes formed by doped portions of said polycrystalline semiconductor layer, said insulating gate field effect transistor in which said conductive region constitutes at least part of the gate electrode being formed as a load transistor and having the gate electrode connected to the drain region.
Claim 13
Dependent Claim
62 words
A method as in claim 10, wherein said integrated circuit comprises two of said transistors formed as loads and having their gate electrodes connected to a common drain region, the gate electrodes of said two transistors comprising laterally diffused conductive regions of said polycrystalline layer of substantially uniform widths and situated at opposite edges of a single part of said polycrystalline layer.
Claim 14
Dependent Claim
75 words
A method as in claim 11, wherein said diffusion step to form said gate electrode conductive regions of the polycrystalline layer is effected in the presence of a masking layer locally present on said part of the polycrystalline layer, said diffusion being carried out simultaneously with the diffusion to form at least part of the source and drain regions of the transistors and to render more highly conductive other exposed portions of the polycrystalline layer.
Claim 15
Dependent Claim
41 words
A method as in claim 12, wherein said masking layer comprises a residual part of a layer provided at the surface of said polycrystalline layer and employed for the previous definition of said polycrystalline layer into a plurality of discrete parts.
Claim 16
Independent Claim
133 words
A method of manufacturing a semiconductor device having low resistivity conductive regions with a substantially uniform narrow line width, said method comprising the steps of: (a) providing a semiconductor element having an insulating layer disposed on at least a surface part thereof, (b) depositing a layer of relatively high resistivity polycrystalline semiconductor material on said insulating layer, (c) forming a masking layer on said polycrystalline layer, (d) removing any exposed portions of said polycrystalline layer such that only edges thereof are exposed throughout the thickness thereof under edge portions of said masking layer, and (e) laterally diffusing a doping element into said polycrystalline layer only at said edges thereof under said masking layer without diffusing said doping element through said insulating layer itself into said semiconductor element, thereby forming said low resistivity regions.
Claim 17
Independent Claim
133 words
A method of manufacturing a semiconductor device having low resistivity conductive regions with a substantially uniform narrow line width, said method comprising the steps of: (a) providing a semiconductor element having an insulating layer disposed on at least a surface part thereof, (b) depositing a layer of relatively high resistivity polycrystalline semiconductor material on said insulating layer, (c) forming a masking layer on said polycrystalline layer, (d) removing any exposed portions of said polycrystalline layer such that only edges thereof are exposed throughout the thickness thereof under edge portions of said masking layer, and (e) laterally diffusing a doping element into said polycrystalline layer only at said edges thereof under said masking layer without diffusing said doping element through said insulating layer itself into said semiconductor element, thereby forming said low resistivity regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-07 | 1985-03-09 | 1985-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-07 | 1989-03-09 | 1989-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-07 | 1993-03-09 | 1993-09-08 | $7700.00 | Window Closed / Lapsed |