Method of fabricating a narrow base-width bipolar device and the product thereof

Claim 1

A method for fabricating a narrow basewidth bipolar semiconductor device having base, emitter and collector regions, comprising the steps of: providing a semiconductor body of a given conductivity type, the body having a common boundary surface; depositing a layer of oxide on the common boundary surface; depositing a layer of polycrystalline silicon on the oxide layer; depositing a layer of masking material on the polycrystalline silicon layer; forming apertures in the masking material; etching the unmasked portions of the polycrystalline silicon layer down to the layer of oxide to expose unetched edges of polycrystalline silicon under the masking layer; doping the exposed edges of the unetched polycrystalline silicon layer to form a narrow line of doped polycrystalline silicon in the polycrystalline silicon layer, the narrow doped line defining the limits of the width of the base region; doping the semiconductor body, through the oxide layer exposed by the etched unmasked portions of the polycrystalline silicon layer, to an opposite conductivity type to form emitter regions; removing the layer of masking material; etching the undoped portions of the polycrystalline silicon layer; doping the semiconductor body, through the oxide layer exposed by the last etched portions of the polycrystalline silicon layer, to an opposite conductivity to form the collector region while simultaneously further doping the emitter regions; and providing the semiconductor body and each doped region with a respective ohmic contact.

Claim 2

A method for fabricating a narrow basewidth bipolar semiconductor device having base, emitter and collector regions, comprising the steps of: providing a semiconductor body of a given conductivity type, the body having a common boundary surface; depositing a layer of oxide on the common boundary surface; depositing a layer of polycrystalline silicon on the oxide layer; depositing a layer of masking material on the polycrystalline silicon layer; forming apertures in the masking material; etching the unmasked portions of the polycrystalline silicon layer down to the layer of oxide to expose unetched edges of polycrystalline silicon under the masking layer; doping the exposed edges of the unetched polycrystalline silicon layer to form a narrow line of doped polycrystalline silicon in the polycrystalline silicon layer, the narrow doped line defining the limits of the width of the base region; doping the semiconductor body, through the oxide layer exposed by the etched unmasked portions of the polycrystalline silicon layer, to an opposite conductivity type to form emitter regions; removing the layer of masking material; etching the undoped portions of the polycrystalline silicon layer; doping the semiconductor body, through the oxide layer exposed by the last etched portions of the polycrystalline silicon layer, to an opposite conductivity to form the collector region while simultaneously further doping the emitter regions; and providing the semiconductor body and each doped region with a respective ohmic contact.