US4069495A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device for integrated injection logic
Assignee: Toshiba Corp
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Filing: 1976-10-05
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Granted: 1978-01-17
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Expires: 1996-10-05
Abstract
Abstract A semiconductor device for integrated injection logic comprises a semiconductor substrate of a first conductivity type, a signal input region of a second conductivity type provided in the substrate, at least one signal output region of the first conductivity type formed in part of the surface of the signal input region, a charge injection region provided closely to the signal input region and forming a pn junction with the substrate and having a higher impurity concentration than the signal input region, and electrodes provided for the substrate, signal input region, signal output region, and charge injection region, respectively. The signal input region includes a first region of the second conductivity type, and a second region provided in at least part of the surface of the first region and having the same conductivity type as that of the first region and having a higher impurity concentration than the first region, said second region being adjoined directly to the signal output region and connected to the signal input electrode.
Inventors
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:33
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D62/13; H10D62/133; H10D62/134; H10D62/137; H10D84/00; H10D84/60; H10D84/65; Y; Y10; Y10S; Y10S148/00; Y10S148/087
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
204 words
A semiconductor device for integrated injection logic comprising a semiconductor substrate of a first conductivity type, a signal input region of a second conductivity type provided in said semiconductor layer of said first conductivity type, at least one signal output region of said first conductivity type formed in said signal input region, a charge injection region of said second conductivity type of high impurity concentration provided closely to said signal input region and forming a pn junction with said semiconductor substrate of said first conductivity type, and electrodes provided for said substrate, signal input region, signal output regions and charge injection region, respectively, wheretby an inverted signal of an input signal is obtained by applying a forward bias voltage to said pn junction, said signal input region including a first portion of said second conductivity type having a lower impurity concentration than said charge injection region and a second portion having the same conductivity type as said first portion and having a higher impurity concentration than said first portion, said second portion being adjoined directly to said signal output region and connected to said signal input electrode, and said first portion being adjoined directly to at least the entire under surface of said portion.
Claim 2
Dependent Claim
204 words
A semiconductor device for integrated injection logic comprising a semiconductor substrate of a first conductivity type, a signal input region of a second conductivity type provided in said semiconductor layer of said first conductivity type, at least one signal output region of said first conductivity type formed in said signal input region, a charge injection region of said second conductivity type of high impurity concentration provided closely to said signal input region and forming a pn junction with said semiconductor substrate of said first conductivity type, and electrodes provided for said substrate, signal input region, signal output regions and charge injection region, respectively, wheretby an inverted signal of an input signal is obtained by applying a forward bias voltage to said pn junction, said signal input region including a first portion of said second conductivity type having a lower impurity concentration than said charge injection region and a second portion having the same conductivity type as said first portion and having a higher impurity concentration than said first portion, said second portion being adjoined directly to said signal output region and connected to said signal input electrode, and said first portion being adjoined directly to at least the entire under surface of said portion.
Claim 3
Dependent Claim
28 words
A semiconductor device according to claim 1, wherein the thickness of said second portion of said signal input region is smaller than that of said signal output region.
Claim 4
Dependent Claim
45 words
A semiconductor device according to claim 1, wherein the thickness of said second portion of said signal input region is greater than that of said signal output region, said second portion being adjoined to a side face and an underside of said signal output region.
Claim 5
Dependent Claim
81 words
A semiconductor device according to claim 1, wherein said first portion and second portion of said signal input region are so disposed as to permit their respective upper and lower surfaces to everywhere interface at the same level, and said signal output region is so disposed that its lower surface is substantially at the same level; whereby part of its side face is adjoined directly to said second portion and the remaining part thereof is adjoined directly to said first portion.
Claim 6
Dependent Claim
91 words
A semiconductor device according to claim 1, said second portion of said signal input region surrounds the side face of said signal output region and is thicker than said signal output region; and of the interfaces between said semiconductor substrate and the underside of said first portion of said signal input region a first interface opposed to the underside of said signal output region is situated nearer to the surface of said semiconductor device than a second interface opposed to the underside of said second portion of said signal input region.
Claim 7
Dependent Claim
148 words
A semiconductor device according to claim 1, wherein said second portion of said signal input region surrounds the side face and underside of said signal output region, and the thickness of that part of said second portion which surrounds said side face of said signal output region is greater than the sum of the thickness of that portion of said second portion which surrounds said underside of said signal output region and the thickness of said signal output region; and of the interfaces between said semiconductor substrate and the underside of said first portion of said signal input region a first interface opposed to the underside of said signal output region is situated nearer to the surface of said semiconductor device than a second interface opposed to the underside of that second portion of said signal input region which surrounds the side face of said signal output region.
References Cited (Backward Citations)
US3962717A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-16 | 1981-07-18 | 1982-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-16 | 1985-07-18 | 1986-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-16 | 1989-07-18 | 1990-01-17 | $7700.00 | Window Closed / Lapsed |