Ultra high density flash memory having vertically stacked devices

Claim 2

A memory cell, comprising: a pillar of semiconductor material extending outwardly from a working surface of a substrate to form source/drain and body regions, the pillar having a number of sides; at least one pair of vertically stacked floating gates, each pair associated with a side of the pillar, a dielectric disposed between the floating gates within each pair; and one or more control gates, each control gate associated with at least one floating gate so as to allow selective storage and retrieval of data on the floating gates.

Claim 3

The memory cell of claim 1, wherein the substrate is a bulk semiconductor.

Claim 4

The memory cell of claim 1, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.

Claim 5

The memory cell of claim 1, wherein the control gate is configured and arranged to store more than two charge states on its associated floating gate.

Claim 6

A memory device, comprising: an array of memory cells, each cell including a number of transistors formed around a common pillar of semiconductor material that forms source/drain and body regions for the transistors and at least one pair of vertically stacked floating gates disposed adjacent to the sides of the pillar; a plurality of control gate lines that are substantially parallel in a first direction, each control gate line allowing selective storage and retrieval of data on ones of the floating gates; at least two source/drain interconnection lines, each source/drain interconnection line interconnecting ones of the source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the source/drain regions of ones of the memory cells.

Claim 7

A memory device, comprising: an array of memory cells, each cell including a number of transistors formed around a common pillar of semiconductor material that forms source/drain and body regions for the transistors and at least one pair of vertically stacked floating gates disposed adjacent to the sides of the pillar; a plurality of control gate lines that are substantially parallel in a first direction, each control gate line allowing selective storage and retrieval of data on ones of the floating gates; at least two source/drain interconnection lines, each source/drain interconnection line interconnecting ones of the source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the source/drain regions of ones of the memory cells.

Claim 8

The memory device of claim 5, wherein the pillar extends outwardly from a bulk semiconductor substrate.

Claim 9

The memory device of claim 5, wherein the pillar extends outwardly from an insulating layer portion formed on top of an underlying semiconductor substrate.

Claim 10

A memory cell that is fabricated upon a substrate, the memory cell comprising: a semiconductor pillar of a first conductivity type formed upon the substrate and having top and side surfaces; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a third source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and between the first and the second source/drain regions; a gate dielectric formed on at least a portion of the side surface of the pillar; at least one pair of vertically stacked floating gates, each pair substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; one or more control gate lines, each of which is substantially adjacent to at least one of the floating gates and insulated therefrom; and an intergate dielectric, interposed between each of the substantially adjacent floating and control gate lines.

Claim 11

A memory cell that is fabricated upon a substrate, the memory cell comprising: a semiconductor pillar of a first conductivity type formed upon the substrate and having top and side surfaces; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a third source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and between the first and the second source/drain regions; a gate dielectric formed on at least a portion of the side surface of the pillar; at least one pair of vertically stacked floating gates, each pair substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; one or more control gate lines, each of which is substantially adjacent to at least one of the floating gates and insulated therefrom; and an intergate dielectric, interposed between each of the substantially adjacent floating and control gate lines.

Claim 12

The memory cell of claim 8, wherein the substrate includes a bulk semiconductor from which the pillar outwardly extends.

Claim 13

The memory cell of claim 8, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

Claim 14

A nonvolatile memory array that is fabricated upon a substrate, the memory array comprising: a plurality of memory cells, each memory cell including: a semiconductor pillar of a first conductivity type formed upon the substrate and having top and side surfaces; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a third source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and between the first and the second source/drain regions; a gate dielectric, formed on at least a portion of the side surface of the pillar; at least one pair of vertically stacked floating gates, each pair substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; at least one control gate line, substantially adjacent to at least one of the floating gates and insulated therefrom; and an intergate dielectric, interposed between each of the substantially adjacent floating gates and control gate lines; one or more first source/drain interconnection lines interconnecting ones of the first source/drain regions of ones of the memory cells; one or more second source/drain interconnection lines interconnecting ones of the second source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the third source/drain regions of ones of the memory cells.

Claim 15

A nonvolatile memory array that is fabricated upon a substrate, the memory array comprising: a plurality of memory cells, each memory cell including: a semiconductor pillar of a first conductivity type formed upon the substrate and having top and side surfaces; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a third source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and between the first and the second source/drain regions; a gate dielectric, formed on at least a portion of the side surface of the pillar; at least one pair of vertically stacked floating gates, each pair substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; at least one control gate line, substantially adjacent to at least one of the floating gates and insulated therefrom; and an intergate dielectric, interposed between each of the substantially adjacent floating gates and control gate lines; one or more first source/drain interconnection lines interconnecting ones of the first source/drain regions of ones of the memory cells; one or more second source/drain interconnection lines interconnecting ones of the second source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the third source/drain regions of ones of the memory cells.

Claim 16

The memory array of claim 11, wherein the substrate includes a bulk semiconductor from which the pillar outwardly extends.

Claim 17

The memory array of claim 11, wherein the substrate includes an insulating layer from which the pillar outwardly extends.