Stacked capacitor doping technique making use of rugged polysilicon

Claim 1

A process for fabricating a capacitor for a storage cell within a DRAM array on a silicon substrate, said process comprising: a) creating a conductively-doped digit line junction and storage node junction, within active areas on opposite sides of a word line; b) depositing a first dielectric layer superjacent said substrate having said digit line and storage node junctions; c) creating first aligned buried contact locations at said digit line junctions in said active areas; d) depositing a first conductive layer superjacent said substrate surface, said first conductive layer making direct contact to said digit line junctions at said first buried contact locations; e) depositing a second dielectric layer superjacent to said first conductive layer; f) masking and etching said first conductive layer and said second dielectric layer to form a plurality of parallel conductive digit lines aligned along columns such that a digit line makes electrical contact at digit line junctions within a column, said digit lines running perpendicular to and over said word lines forming a three-dimensional, waveform-like topology having an array surface; g) depositing a third dielectric layer superjacent said array surface of said waveform-like topology; h) depositing a subsequent dielectric layer containing a first dopant type, superjacent said third dielectric layer; i) creating a second aligned buried contact location at said storage node junctions in said active areas; j) depositing a second conductive layer superjacent said array surface, whereby the second conductive layer assumes said waveform-like topology in response to existing topology, said second conductive layer making contact to said storage node junctions at said second buried contact locations; k) doping said second conductive layer via said previously deposited doped dielectric; l) patterning said second conductive layer to form storage node plates at said storage node junctions; m) depositing a cell dielectric layer adjacent and coextensive with said storage node plates and adjacent said array surface; and n) depositing a third conductive layer adjacent and coextensive with said cell dielectric layer to form a cell plate common to the entire memory array.