Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface

Claim 2

A process for fabricating an integrated circuit structure on a substrate, comprising: depositing a conductive layer of amorphous silicon on said substrate; depositing a dielectric layer on said conductive layer of amorphous silicon in such a manner as to define an interface between said dielectric layer and said conductive layer of amorphous silicon of extreme smoothness having a roughness factor measured by a maximum local excursion in either direction normal to said interface no greater than 60 angstroms; and crystallizing said conductive layer of amorphous silicon to form polycrystalline silicon as said conductive layer, while maintaining the smoothness of said interface between said dielectric layer and said conductive layer of polycrystalline silicon with a roughness factor measured by a maximum local excursion in either direction normal to said interface no greater than 60 angstroms.

Claim 3

A process as set forth in claim 1, wherein the dielectric layer is deposited on said conductive layer of amorphous silicon by low pressure chemical vapor deposition.

Claim 4

A process as set forth in claim 2, further including: implanting a dopant material in the conductive layer of amorphous silicon subsequent to the deposition thereof on said substrate.

Claim 5

A process as set forth in claim 3, wherein said conductive layer of amorphous silicon is deposited on said substrate in the amorphous phase at 560 degrees C.

Claim 6

A process for fabricating an integrated circuit structure on a substrate, comprising: depositing a first conductive layer of amorphous silicon on said substrate; depositing a dielectric layer on said first conductive layer of amorphous silicon in such a manner as to define a smooth first interface between said dielectric layer and said first conductive layer of amorphous silicon of extreme smoothness having a roughness factor measured by a maximum local excursion in either direction normal to said first interface no greater than 60 angstroms; crystallizing said first conductive layer of amorphous silicon to form polycrystalline silicon as said first conductive layer, while maintaining the smoothness of said first interface between said dielectric layer and said first conductive layer of polycrystalline silicon with a roughness factor measured by a maximum local excursion in either direction normal to said first interface no greater than 60 angstroms; and depositing a second conductive layer on said dielectric layer in such a manner as to define a smooth second interface between said dielectric layer and said second conductive layer.

Claim 7

A process for fabricating an integrated circuit structure on a substrate, comprising: depositing a first conductive layer of amorphous silicon on said substrate; depositing a dielectric layer on said first conductive layer of amorphous silicon in such a manner as to define a smooth first interface between said dielectric layer and said first conductive layer of amorphous silicon of extreme smoothness having a roughness factor measured by a maximum local excursion in either direction normal to said first interface no greater than 60 angstroms; crystallizing said first conductive layer of amorphous silicon to form polycrystalline silicon as said first conductive layer, while maintaining the smoothness of said first interface between said dielectric layer and said first conductive layer of polycrystalline silicon with a roughness factor measured by a maximum local excursion in either direction normal to said first interface no greater than 60 angstroms; and depositing a second conductive layer on said dielectric layer in such a manner as to define a smooth second interface between said dielectric layer and said second conductive layer.

Claim 8

A process as set forth in claim 5, wherein each of said first conductive layer of amorphous silicon, said dielectric layer, and said second conductive layer is respectively deposited by low pressure chemical vapor deposition.

Claim 9

A process as set forth in claim 6, further including: implanting a dopant material in the first conductive layer of amorphous silicon subsequent to the deposition thereof on said substrate.

Claim 10

A process as set forth in claim 7, wherein said first conductive layer of amorphous silicon is deposited on said substrate in the amorphous phase at 560 degrees C.

Claim 11

A process as set forth in claim 5, wherein the deposition of said dielectric layer on said first conductive layer of amorphous silicon comprises: depositing a multi-layer dielectric film including depositing by low pressure chemical vapor deposition a first dielectric film of silicon oxide, depositing by low pressure chemical vapor deposition a second dielectric film of silicon nitride on said first dielectric film of silicon oxide to define a dual-film dielectric, subjecting the dual-film dielectric to oxidation, and converting a portion of the silicon nitride film onto a silicon oxynitride film in response to the oxidation to define a triple-layer dielectric film.

Claim 12

A process as set forth in claim 9, wherein crystallizing of the first conductive layer of amorphous silicon to form polycrystalline silicon as the first conductive layer is accomplished by annealing the first conductive layer of amorphous silicon simultaneously with the oxidation of the dual-film dielectric in converting part of the silicon nitride film into a silicon oxynitride film.

Claim 13

A process as set forth in claim 9, wherein said multi-layer dielectric film is of the order of 400 angstroms in thickness.

Claim 14

A process for fabricating an integrated circuit structure on a substrate, wherein said substrate is of semiconductor material of one conductivity type; said process comprising: depositing dopant material of the other conductivity type in the semiconductor substrate in first and second regions thereof in spaced relation with respect to each other and to define first and second regions of the other conductivity type in said substrate with a space forming a channel therebetween; depositing an insulating layer on said semiconductor substrate in the space between said first and second regions of the other conductivity type and extending in overlying relation to the channel formed by the portion of the semiconductor substrate of one conductivity type between said first and second regions; depositing a first conductive layer of amorphous silicon on said insulating layer defining a floating gate overlying and capacitively coupled to the channel of said one conductivity type; depositing a dielectric layer on the first conductive layer of amorphous silicon in such a manner as to define a smooth first interface between said dielectric layer and said first conductive layer of amorphous silicon of extreme smoothness having a roughness factor measured by a maximum local excursion in either direction normal to said first interface no greater than 60 angstroms; crystallizing said first conductive layer of amorphous silicon to form polycrystalline silicon as said first conductive layer while maintaining the smoothness of said first interface between said dielectric layer and said first conductive layer of polycrystalline silicon with a roughness factor measured by a maximum local excursion in either direction normal to said first interface no greater than 60 angstroms; and depositing a second conductive layer on said dielectric layer in such a manner as to define a smooth second interface between said dielectric layer and said second conductive layer such that a non-volatile memory cell is produced in which the second conductive layer defines a control gate capacitively coupled to a floating gate as defined by said first conductive layer of polycrystalline silicon via said dielectric layer interposed therebetween.

Claim 15

A process for fabricating an integrated circuit structure on a substrate, wherein said substrate is of semiconductor material of one conductivity type; said process comprising: depositing dopant material of the other conductivity type in the semiconductor substrate in first and second regions thereof in spaced relation with respect to each other and to define first and second regions of the other conductivity type in said substrate with a space forming a channel therebetween; depositing an insulating layer on said semiconductor substrate in the space between said first and second regions of the other conductivity type and extending in overlying relation to the channel formed by the portion of the semiconductor substrate of one conductivity type between said first and second regions; depositing a first conductive layer of amorphous silicon on said insulating layer defining a floating gate overlying and capacitively coupled to the channel of said one conductivity type; depositing a dielectric layer on the first conductive layer of amorphous silicon in such a manner as to define a smooth first interface between said dielectric layer and said first conductive layer of amorphous silicon of extreme smoothness having a roughness factor measured by a maximum local excursion in either direction normal to said first interface no greater than 60 angstroms; crystallizing said first conductive layer of amorphous silicon to form polycrystalline silicon as said first conductive layer while maintaining the smoothness of said first interface between said dielectric layer and said first conductive layer of polycrystalline silicon with a roughness factor measured by a maximum local excursion in either direction normal to said first interface no greater than 60 angstroms; and depositing a second conductive layer on said dielectric layer in such a manner as to define a smooth second interface between said dielectric layer and said second conductive layer such that a non-volatile memory cell is produced in which the second conductive layer defines a control gate capacitively coupled to a floating gate as defined by said first conductive layer of polycrystalline silicon via said dielectric layer interposed therebetween.

Claim 16

A process as set forth in claim 12, wherein the deposition of said dielectric layer upon said first conductive layer of amorphous silicon is accomplished in such a manner as to provide said smooth first interface therebetween with a maximum local excursion in either direction normal to said first interface no greater than 10 percent of the thickness of said dielectric layer.

Claim 17

A process as set forth in claim 12, wherein each of said first conductive layer of amorphous silicon, said dielectric layer, and said second conductive layer is respectively deposited by low pressure chemical vapor deposition.

Claim 18

A process as set forth in claim 14, further including: implanting a dopant material in the first conductive layer of amorphous silicon subsequent to the deposition thereof on said insulating layer.

Claim 19

A process as set forth in claim 12, wherein the deposition of said dielectric layer on said first conductive layer of amorphous silicon comprises: depositing a multi-layer dielectric film including depositing by low pressure chemical vapor deposition a first dielectric film of silicon oxide, depositing by low pressure chemical vapor deposition a second dielectric film of silicon nitride on said first dielectric film of silicon oxide to define a dual-film dielectric, subjecting the dual-film dielectric to oxidation, and converting a portion of the silicon nitride film into a silicon oxynitride film in response to the oxidation to define a triple-layer dielectric film.

Claim 20

A process as set forth in claim 16, wherein crystallizing of the first conductive layer of amorphous silicon to form polycrystalline silicon as the first conductive layer is accomplished by annealing the first conductive layer of amorphous silicon simultaneously with the oxidation of the dual-film dielectric in converting part of the silicon nitride film into a silicon oxynitride film.