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US4742018A
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Process for producing memory cell having stacked capacitor
Assignee: Hitachi Ltd
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Filing: 1986-12-01
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Granted: 1988-05-03
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Expires: 2006-12-01
Abstract
Abstract A process for producing a memory cell having a stacked capacitor. As the reduction in device size of memory cells progresses, it becomes difficult to obtain a satisfactorily large capacitance even with a stacked capacitor structure. To enable a larger capacitance to be obtained for the same occupied area, projections and recesses are provided on the surface of a capacitor electrode. It is possible, according to the process, to readily produce projections and recesses for increasing the storage capacitance.
Inventors
- 👤 Shinichiro Kimura
- 👤 Hideo Sunami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:46
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/714; Y; Y10; Y10S; Y10S148/00; Y10S148/014
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
153 words
A process for producing a dynamic random access memory cell having a stacked capacitor, comprising the steps of: forming a MOSFET having a gate electrode, a drain region and a source region, the drain and source regions being formed in a semiconductor substrate; forming a first conductor layer on said semiconductor substrate so that said first conductor layer is electrically connected to said drain region; depositing a first insulator film on said first conductor layer and removing said first insulator film except for a necessary portion; depositing a second conductor layer on said first insulator so that said second conductor layer is electrically connected to said first conductor layer, and removing said second conductor layer except for a necessary portion; removing said first insulator film alone; forming a second insulator film on the respective surfaces of said first and second conductor layers; and forming a third conductor layer on said second insulator film.
Claim 2
Dependent Claim
153 words
A process for producing a dynamic random access memory cell having a stacked capacitor, comprising the steps of: forming a MOSFET having a gate electrode, a drain region and a source region, the drain and source regions being formed in a semiconductor substrate; forming a first conductor layer on said semiconductor substrate so that said first conductor layer is electrically connected to said drain region; depositing a first insulator film on said first conductor layer and removing said first insulator film except for a necessary portion; depositing a second conductor layer on said first insulator so that said second conductor layer is electrically connected to said first conductor layer, and removing said second conductor layer except for a necessary portion; removing said first insulator film alone; forming a second insulator film on the respective surfaces of said first and second conductor layers; and forming a third conductor layer on said second insulator film.
Claim 3
Dependent Claim
29 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 1, wherein each of said steps is carried out at least once.
Claim 4
Dependent Claim
32 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 1, wherein said second insulator film contains at least either silicon oxide or silicon nitride.
Claim 5
Dependent Claim
31 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 3, wherein said third conductor layer is formed by low pressure chemical vapor deposition.
Claim 6
Dependent Claim
33 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 1, wherein the first insulator film is removed alone by isotropically etching the first insulator film.
Claim 7
Dependent Claim
43 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 1, wherein the first, second and third conductor layers are made of conductive materials selected from the group consisting of Al, W, Ti and silicides thereof.
Claim 8
Dependent Claim
36 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 1, wherein each of the first, second and third conductor layers are formed of polycrystalline silicon doped with impurities.
Claim 9
Dependent Claim
62 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 7, wherein the drain region is of a first conductivity type, and wherein the first and second conductor layers are doped with impurities such that each of the first and second conductor layers are of the same conductivity types as that of the drain region.
Claim 10
Dependent Claim
36 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 1, wherein the second conductor layer is formed on top of the necessary portion of the first insulator film.
Claim 11
Dependent Claim
37 words
A process for producing a dynamic random access memory cell having a stacked capacitor according to claim 1, wherein the second conductor layer is formed at the sides of the necessary portion of the first insulator film.
References Cited (Backward Citations)
US4355374A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-03 | 1991-11-02 | 1992-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-03 | 1995-11-02 | 1996-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-03 | 1999-11-02 | 2000-05-03 | $7700.00 | Window Closed / Lapsed |