US5636170A
Expired / Lapsed
US
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Low voltage dynamic memory
Assignee: Micron Technology Inc
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Filing: 1995-11-13
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Granted: 1997-06-03
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Expires: 2015-11-13
Abstract
Abstract A low voltage high density memory device is described. The memory device uses isolation transistors to adjust the voltage stored on memory cells. The memory device is designed to reduce the differential voltage between memory cells storing different data states. A method is described for reducing leakage current of the memory cells to decrease the need for excessive refresh operations. The memory device is described as operating on a one volt supply and producing a 250 mv digit line swing.
Inventors
- 👤 Mirmajid Seyyedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:43
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C7/00; G11C7/06; G11C7/065; G11C7/10; G11C7/1006; G11C7/12
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
123 words
An integrated memory circuit comprising: a plurality of memory cell capacitors; a plurality of access devices connected between the plurality of memory cell capacitors and a communication line, each for selectively connecting one of the plurality of memory cell capacitors to the communication line; a sense amplifier circuit; and an n-type isolation transistor and a p-type isolation transistor electrically located between the sense amplifier circuit and the communication line, the integrated memory circuit is adapted to store a maximum charge on the one of the plurality of memory cells which is less than an upper supply voltage level, and adapted to store a minimum charge on the one of the plurality of memory cells which is greater than a lower supply voltage level.
Claim 2
Dependent Claim
123 words
An integrated memory circuit comprising: a plurality of memory cell capacitors; a plurality of access devices connected between the plurality of memory cell capacitors and a communication line, each for selectively connecting one of the plurality of memory cell capacitors to the communication line; a sense amplifier circuit; and an n-type isolation transistor and a p-type isolation transistor electrically located between the sense amplifier circuit and the communication line, the integrated memory circuit is adapted to store a maximum charge on the one of the plurality of memory cells which is less than an upper supply voltage level, and adapted to store a minimum charge on the one of the plurality of memory cells which is greater than a lower supply voltage level.
Claim 3
Dependent Claim
40 words
The integrated memory circuit of claim 1 wherein the plurality of access devices comprise an n-type access transistor having a source connected to one plate of the plurality of memory cell capacitors, and a drain connected to the communication line.
Claim 4
Dependent Claim
17 words
The integrated memory circuit of claim 2 wherein the n-type access transistor is fabricated in a p-well.
Claim 5
Dependent Claim
18 words
The integrated memory circuit of claim 3 wherein the p-well is electrically biased to a non-zero voltage level.
Claim 6
Dependent Claim
30 words
The integrated memory circuit of claim 1 wherein the n-type isolation transistor has a gate selectively coupled to either an upper supply rail (Vcc) or a lower supply rail (Vss).
Claim 7
Dependent Claim
30 words
The integrated memory circuit of claim 1 wherein the p-type isolation transistor has a gate selectively coupled to either an upper supply rail (Vcc) or a lower supply rail (Vss).
Claim 8
Dependent Claim
117 words
An integrated memory circuit comprising: memory cell capacitors having one plate connected to a source of n-type access transistors, the n-type access transistors having a drain connected to a digit line; a sense amplifier circuit; and an n-type isolation transistor and a p-type isolation transistor electrically located between the sense amplifier circuit and the digit line, the integrated memory circuit is adapted to store a maximum charge on a memory cell which is a p-type transistor threshold voltage less than an upper supply voltage level (Vcc-V TN ), and adapted to store a minimum charge on the memory cell which is a p-type transistor threshold voltage level greater than a lower supply voltage level (Vss+V TP ).
Claim 9
Dependent Claim
117 words
An integrated memory circuit comprising: memory cell capacitors having one plate connected to a source of n-type access transistors, the n-type access transistors having a drain connected to a digit line; a sense amplifier circuit; and an n-type isolation transistor and a p-type isolation transistor electrically located between the sense amplifier circuit and the digit line, the integrated memory circuit is adapted to store a maximum charge on a memory cell which is a p-type transistor threshold voltage less than an upper supply voltage level (Vcc-V TN ), and adapted to store a minimum charge on the memory cell which is a p-type transistor threshold voltage level greater than a lower supply voltage level (Vss+V TP ).
Claim 10
Dependent Claim
45 words
The integrated memory circuit of claim 7 wherein the n-type isolation transistor has a drain connected to the sense amplifier circuit and a source connected to a source of the p-type isolation transistor, the p-type isolation transistor having a drain connected to the digit line.
Claim 11
Dependent Claim
24 words
The integrated memory circuit of claim 8 wherein the n-type access transistor is fabricated in a p-well electrically biased to a non-zero voltage level.
Claim 12
Dependent Claim
53 words
The integrated memory circuit of claim 7 wherein: the n-type isolation transistor has a gate selectively coupled to either an upper supply rail (Vcc) or a lower supply rail (Vss), and the p-type isolation transistor has a gate selectively coupled to either an upper supply rail (Vcc) or a lower supply rail (Vss).
Claim 13
Dependent Claim
17 words
The integrated memory circuit of claim 10 wherein Vcc is approximately one volt and Vss is ground.
Claim 14
Independent Claim
66 words
A method of storing data in an integrated memory device, the method comprising the steps of: storing a reduced voltage on a first memory capacitor, where the reduced voltage is an n-channel transistor threshold voltage level below a supply voltage; and storing an increased voltage on a second memory capacitor, where the increased voltage is a p-channel transistor threshold voltage level above a lower reference voltage.
Claim 15
Independent Claim
66 words
A method of storing data in an integrated memory device, the method comprising the steps of: storing a reduced voltage on a first memory capacitor, where the reduced voltage is an n-channel transistor threshold voltage level below a supply voltage; and storing an increased voltage on a second memory capacitor, where the increased voltage is a p-channel transistor threshold voltage level above a lower reference voltage.
Claim 16
Dependent Claim
19 words
The method of claim 12 further including the step of: adjusting a substrate bias voltage to minimize leakage currents.
Claim 17
Dependent Claim
41 words
The method of claim 13 wherein the step of adjusting the substrate bias voltage comprises the steps of: lowering the substrate bias voltage to lower a sub-threshold leakage current; and raising the substrate bias voltage to lower a junction leakage current.
Claim 18
Dependent Claim
20 words
The method of claim 12 wherein the supply voltage is approximately one volt, and the lower reference voltage is ground.
Claim 19
Independent Claim
118 words
A method of storing data in a memory device, the method comprising the steps of: providing a supply voltage to a source and gate of an n-channel transistor, the supply voltage being approximately one volt; coupling a drain of the n-channel transistor to a first memory cell, such that the first memory cell is charged to a voltage level which is an n-channel transistor threshold voltage level below the supply voltage; connecting a drain and gate of a p-channel transistor to ground; and coupling a source of the p-channel transistor to a second memory cell, such that the second memory cell is charged to a voltage level which is a p-channel transistor threshold voltage level above the ground.
Claim 20
Independent Claim
118 words
A method of storing data in a memory device, the method comprising the steps of: providing a supply voltage to a source and gate of an n-channel transistor, the supply voltage being approximately one volt; coupling a drain of the n-channel transistor to a first memory cell, such that the first memory cell is charged to a voltage level which is an n-channel transistor threshold voltage level below the supply voltage; connecting a drain and gate of a p-channel transistor to ground; and coupling a source of the p-channel transistor to a second memory cell, such that the second memory cell is charged to a voltage level which is a p-channel transistor threshold voltage level above the ground.
Claim 21
Dependent Claim
19 words
The method of claim 16 further including the step of: adjusting a substrate bias voltage to minimize leakage currents.
Claim 22
Dependent Claim
41 words
The method of claim 17 wherein the step of adjusting the substrate bias voltage comprises the steps of: lowering the substrate bias voltage to lower a sub-threshold leakage current; and raising the substrate bias voltage to lower a junction leakage current.
References Cited (Backward Citations)
US5414662A
Cited
US5444662A
Cited
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| 3.5 Years (Year 4) | 2000-06-02 | 2000-12-02 | 2001-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-02 | 2004-12-02 | 2005-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-02 | 2008-12-02 | 2009-06-03 | $7700.00 | Window Closed / Lapsed |