High density data storage using stacked wafers

Claim 2

A stacked wafer device comprising: (a) a plurality of semiconductor wafers arranged in a stack; (b) each wafer having a plurality of connection pads formed on the upper face of the wafer, the connection pads made of a first metallic material; (c) each wafer further having a plurality through-holes axially aligned with the connection pads, each through-hole extending through the wafer to an opposite face of the wafer; (d) each wafer further including a plurality of solid bumps of a second metallic material, each bump engaging and making electrical contact with a connection pad formed on the wafer at an interface and extending through the through-hole of another wafer to make electrical contact with a connection pad formed on the other wafer; (e) the first and second metallic materials selected such that the metallic materials do not form a rigid mechanical bond at the interface between the connection pad and the bump.

Claim 3

The device of claim 1 wherein the first metallic material comprises aluminum and the second metallic material comprises a malleable metal.

Claim 4

The device of claim 2 wherein the second metallic material comprises gold.

Claim 5

The device of claim 1 further including means for applying a mechanical force to the stack of wafers in a direction substantially perpendicular to the interface between the connection pad and the bump.

Claim 6

The device of claim 4 wherein the means for applying a mechanical force comprises a spring.

Claim 7

The memory device of claim 1 wherein each solid bump makes electrical contact to an interior semiconductor region beneath one of said connection pads.

Claim 8

A stacked wafer memory device comprising: (a) a stack of semiconductor wafers, each wafer including a plurality of memory unit pairs arranged in a regular pattern, the memory unit pairs having a generally rectangular configuration; (b) each of the memory unit pairs having four power supply connection areas, one positioned at each corner of the rectangle; two clock connection areas positioned on first opposing sides of the rectangle; two ground connection areas positioned on second opposing sides of the rectangle; and a combined address and input and output connection area, positioned substantially in the center of the rectangle; (c) each wafer having a plurality of connection pads formed on the upper face of the wafer at positions defined by the connection areas, the connection pads comprising a first metallic material; (d) each wafer further having a plurality through-holes axially aligned with the connection pads, each through-hole extending through the wafer to an opposite face of the wafer; (e) each wafer further including a plurality of solid bumps of a second metallic material, each bump engaging and making electrical contact with a connection pad formed on the wafer at an interface and extending through the through-hole of another wafer to make electrical contact with a connection pad formed on the other wafer; (f) the first and second metallic materials selected such that the metallic materials do not form a rigid mechanical bond at the interface between the connection pad and the bump.

Claim 9

A stacked wafer memory device comprising: (a) a stack of semiconductor wafers, each wafer including a plurality of memory unit pairs arranged in a regular pattern, the memory unit pairs having a generally rectangular configuration; (b) each of the memory unit pairs having four power supply connection areas, one positioned at each corner of the rectangle; two clock connection areas positioned on first opposing sides of the rectangle; two ground connection areas positioned on second opposing sides of the rectangle; and a combined address and input and output connection area, positioned substantially in the center of the rectangle; (c) each wafer having a plurality of connection pads formed on the upper face of the wafer at positions defined by the connection areas, the connection pads comprising a first metallic material; (d) each wafer further having a plurality through-holes axially aligned with the connection pads, each through-hole extending through the wafer to an opposite face of the wafer; (e) each wafer further including a plurality of solid bumps of a second metallic material, each bump engaging and making electrical contact with a connection pad formed on the wafer at an interface and extending through the through-hole of another wafer to make electrical contact with a connection pad formed on the other wafer; (f) the first and second metallic materials selected such that the metallic materials do not form a rigid mechanical bond at the interface between the connection pad and the bump.

Claim 10

The memory device of claim 7 wherein the first metallic material comprises aluminum and the second metallic material comprises a malleable metal.

Claim 11

The memory device of claim 8 wherein the second metallic material comprises gold.

Claim 12

The memory device of claim 7 wherein each bump is isolated from the other wafer by an insulator coating on the sidewalls of a through-hole.

Claim 13

The memory device of claim 7 wherein each solid bump makes electrical contact to an interior semiconductor region beneath one of said connection pads.

Claim 14

The memory device of claim 7 wherein each power supply and clock connection area is shared by four memory units and each ground and combined address and input and output connection area is shared by two memory units.

Claim 15

A stacked wafer memory device comprising: (a) a stack of semiconductor wafers, each wafer including a plurality of memory unit pairs arranged in a regular pattern, the memory unit pairs having a generally rectangular configuration; (b) each of the memory unit pairs having four power supply connection areas, one positioned at each corner of the rectangle; two clock connection areas positioned on first opposing sides of the rectangle; two ground connection areas positioned on second opposing sides of the rectangle; and a combined address and input and output connection areas, positioned substantially in the center of the rectangle; (c) each wafer having a plurality of connection pads formed on the upper face of the wafers at positions defined by the connection areas, the connection pads comprising aluminum; (d) each wafer further having a plurality through-holes axially aligned with the connection pads, each through-hole extending through the wafer to an opposite face of the wafer; (e) each wafer further including a plurality of solid bumps comprising gold, each bump engaging and making electrical contact with a connection pad formed on the wafer at an interface and extending through the through-hole of another wafer to make electrical contact with a connection pad formed on the other wafer; the bump isolated from the other wafer by an insulator coating on the sidewalls of the through-hole; (f) wherein the aluminum pad and the gold bump do not form a rigid mechanical bond at the interface between the connection pad and the bump; and (g) means for applying a mechanical force to the stack of wafers in a direction substantially perpendicular to the interface between the connection pad and the bump.

Claim 16

A stacked wafer memory device comprising: (a) a stack of semiconductor wafers, each wafer including a plurality of memory unit pairs arranged in a regular pattern, the memory unit pairs having a generally rectangular configuration; (b) each of the memory unit pairs having four power supply connection areas, one positioned at each corner of the rectangle; two clock connection areas positioned on first opposing sides of the rectangle; two ground connection areas positioned on second opposing sides of the rectangle; and a combined address and input and output connection areas, positioned substantially in the center of the rectangle; (c) each wafer having a plurality of connection pads formed on the upper face of the wafers at positions defined by the connection areas, the connection pads comprising aluminum; (d) each wafer further having a plurality through-holes axially aligned with the connection pads, each through-hole extending through the wafer to an opposite face of the wafer; (e) each wafer further including a plurality of solid bumps comprising gold, each bump engaging and making electrical contact with a connection pad formed on the wafer at an interface and extending through the through-hole of another wafer to make electrical contact with a connection pad formed on the other wafer; the bump isolated from the other wafer by an insulator coating on the sidewalls of the through-hole; (f) wherein the aluminum pad and the gold bump do not form a rigid mechanical bond at the interface between the connection pad and the bump; and (g) means for applying a mechanical force to the stack of wafers in a direction substantially perpendicular to the interface between the connection pad and the bump.

Claim 17

The memory device of claim 13 wherein each solid bump makes electrical contact to an interior semiconductor region beneath one of said connection pads.