Semiconductor integrated circuit device

Claim 1

A semiconductor integrated circuit device comprising: a semiconductor body having a top surface, said semiconductor body having a plurality of vertically elongated grooves provided therein opening onto the top surface thereof; said semiconductor body including a lower semiconductor portion of one conductivity type and an upper semiconductor portion of the other conductivity type; said plurality of vertically elongated grooves extending into said lower semiconductor portion of one conductivity type; a plurality of regions of said one conductivity type provided in said upper semiconductor portion of the other conductivity type and opening onto the top surface of said semiconductor body, said plurality of regions being arranged in groups defining respective rows of said regions of said one conductivity type; an insulation lining disposed in each of said grooves and covering the groove-defining surfaces of said semiconductor body; a conductive material filling each of said grooves and being insulated from said semiconductor body by said insulation lining in said grooves; an insulation layer disposed on said top surface of said semiconductor body and including spaced apart insulation portions of increased thickness, the remaining portions of said insulation layer being relatively thin in relation to said insulation portions of increased thickness; each of said insulation portions of increased thickness extending above the upper surface and below the lower surface of said relatively thin remaining portions of said insulation layer, each of said insulation portions of increased thickness further being interposed between adjacent regions of said one conductivity type provided in said upper semiconductor portion of the other conductivity type to electrically isolate adjacent ones of said regions of said one conductivity type from each other and overlying said conductive material filling each of said grooves; said relatively thin remaining portions of said insulation layer overlying said plurality of regions of said one conductivity type provided in said upper semiconductor portion of the other conductivity type and respectively extending between adjacent insulation portions of increased thickness; a plurality of strips of conductive material overlying said insulation layer in registration with respective rows of said regions of said one conductivity type; said semiconductor body, said conductive material filling each of said grooves in said semiconductor body, said insulation layer and said plurality of strips of conductive material cooperating to define a plurality of memory cells each comprising a transfer gate transistor and a capacitor; the transistor of each memory cell being vertically arranged along the conductive material filling a respective groove and including one of said regions of said one conductivity type as a source region, the upper semiconductor portion of said other conductivity type as a channel region, and the lower semiconductor portion of said one conductivity type as a drain region, with said conductive material filling said groove being a transfer gate; the capacitor of each memory cell including said one region of said one conductivity type forming the source region of said transistor as a first electrode, a respective one of said plurality of strips of conductive material in registration with the row containing said one region of said one conductivity type as a second electrode, and a respective relatively thin portion of said insulation layer as the dielectric layer between said first and second electrodes; and said conductive material filling each of said grooves in said semiconductor body serving as respective word lines and said plurality of strips of conductive material serving as bit lines for the plurality of memory cells.