US5936274A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density flash memory
Assignee: Micron Technology Inc
•
Filing: 1997-07-08
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Granted: 1999-08-10
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Expires: 2017-07-08
Abstract
Abstract A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control gates distributed on opposing sides of the pillar. The control gates are formed together with interconnecting gate lines. First source/drain terminals are row addressable by interconnection lines disposed substantially orthogonal to the gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only 2F 2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than 2F 2 is needed per bit of data.
Inventors
- 👤 Leonard Forbes
- 👤 Wendell P. Noble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:06
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/684; H10D30/685; H10D30/687
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
85 words
A memory cell, comprising: a pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source/drain and body regions wherein the source/drain regions are formed within the pillar, the pillar having a number of sides; a number of floating gates, each gate associated with only one side of the pillar; and a number of control gates, each control gate associated with only one floating gate so as to allow selective storage and retrieval of data on the floating gates.
Claim 2
Dependent Claim
85 words
A memory cell, comprising: a pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source/drain and body regions wherein the source/drain regions are formed within the pillar, the pillar having a number of sides; a number of floating gates, each gate associated with only one side of the pillar; and a number of control gates, each control gate associated with only one floating gate so as to allow selective storage and retrieval of data on the floating gates.
Claim 3
Dependent Claim
24 words
The memory cell of claim 1, wherein the control gate is capable of storing more than two charge states on its associated floating gate.
Claim 4
Dependent Claim
13 words
The memory cell of claim 1, wherein the substrate is a bulk semiconductor.
Claim 5
Dependent Claim
25 words
The memory cell of claim 1, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor substrate.
Claim 6
Dependent Claim
125 words
A memory device, comprising: an array of memory cells, each cell including at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that forms source/drain and body regions for the transistors within the pillar and at least a pair of floating gates disposed adjacent to the opposing sides of the pillar; a plurality of gate lines that are substantially parallel, each gate line allowing selective storage and retrieval of data on ones of the floating gates; at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.
Claim 7
Dependent Claim
125 words
A memory device, comprising: an array of memory cells, each cell including at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that forms source/drain and body regions for the transistors within the pillar and at least a pair of floating gates disposed adjacent to the opposing sides of the pillar; a plurality of gate lines that are substantially parallel, each gate line allowing selective storage and retrieval of data on ones of the floating gates; at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.
Claim 8
Dependent Claim
16 words
The memory device of claim 5, wherein the pillar extends outwardly from a bulk semiconductor substrate.
Claim 9
Dependent Claim
24 words
The memory device of claim 5, wherein the pillar extends outwardly from an insulating layer portion formed on top of an underlying semiconductor substrate.
Claim 10
Dependent Claim
114 words
A memory device, comprising: an array of memory cells, each cell including a number of transistors formed around a common pillar of semiconductor material that forms source/drain and body regions within the pillar for the transistors and a number of gates each disposed adjacent to only one of the sides of the pillar; a plurality of gate lines, each gate line interconnecting ones of the gates in ones of the memory cells; at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.
Claim 11
Dependent Claim
114 words
A memory device, comprising: an array of memory cells, each cell including a number of transistors formed around a common pillar of semiconductor material that forms source/drain and body regions within the pillar for the transistors and a number of gates each disposed adjacent to only one of the sides of the pillar; a plurality of gate lines, each gate line interconnecting ones of the gates in ones of the memory cells; at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.
Claim 12
Dependent Claim
16 words
The memory device of claim 8, wherein the pillar extends outwardly from a bulk semiconductor substrate.
Claim 13
Dependent Claim
24 words
The memory device of claim 8, wherein the pillar extends outwardly from an insulating layer portion formed on top of an underlying semiconductor substrate.
Claim 14
Dependent Claim
139 words
A floating gate transistor that is fabricated upon a substrate, the transistor comprising: a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a gate dielectric formed on at least a portion of one side surface of the pillar; a floating gate, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; a control gate, substantially adjacent to the floating gate and insulated therefrom; and an intergate dielectric, interposed between the floating and control gates.
Claim 15
Dependent Claim
139 words
A floating gate transistor that is fabricated upon a substrate, the transistor comprising: a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a gate dielectric formed on at least a portion of one side surface of the pillar; a floating gate, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; a control gate, substantially adjacent to the floating gate and insulated therefrom; and an intergate dielectric, interposed between the floating and control gates.
Claim 16
Dependent Claim
20 words
The floating gate transistor of claim 11, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.
Claim 17
Dependent Claim
20 words
The floating gate transistor of claim 11, wherein the substrate includes an insulating layer from which the pillar outwardly extends.
Claim 18
Dependent Claim
158 words
A memory cell that is fabricated upon a substrate, the memory cell comprising: a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a gate dielectric formed on at least a portion of only one side surface of the pillar; a plurality of floating gates, each of which is substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; a plurality of control gates, each of which is substantially adjacent to one of the floating gates and insulated therefrom; and an intergate dielectric, interposed between each of the substantially adjacent floating and control gates.
Claim 19
Dependent Claim
158 words
A memory cell that is fabricated upon a substrate, the memory cell comprising: a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a gate dielectric formed on at least a portion of only one side surface of the pillar; a plurality of floating gates, each of which is substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; a plurality of control gates, each of which is substantially adjacent to one of the floating gates and insulated therefrom; and an intergate dielectric, interposed between each of the substantially adjacent floating and control gates.
Claim 20
Dependent Claim
19 words
The memory cell of claim 14, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.
Claim 21
Dependent Claim
19 words
The memory cell of claim 14, wherein the substrate includes an insulating layer from which the pillar outwardly extends.
Claim 22
Dependent Claim
211 words
A nonvolatile memory array that is fabricated upon a substrate, the memory array comprising: a plurality of memory cells, each memory cell including: a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a gate dielectric, formed on at least a portion of only one side surface of the pillar; a floating gate, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; a control gate, substantially adjacent to the floating gate and insulated therefrom; and an intergate dielectric, interposed between the floating gate and the control gate; a plurality of gate lines interconnecting ones of the control gates in ones of the memory cells; at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.
Claim 23
Dependent Claim
211 words
A nonvolatile memory array that is fabricated upon a substrate, the memory array comprising: a plurality of memory cells, each memory cell including: a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate; a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate; a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region; a gate dielectric, formed on at least a portion of only one side surface of the pillar; a floating gate, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric; a control gate, substantially adjacent to the floating gate and insulated therefrom; and an intergate dielectric, interposed between the floating gate and the control gate; a plurality of gate lines interconnecting ones of the control gates in ones of the memory cells; at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.
Claim 24
Dependent Claim
19 words
The memory array of claim 17, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.
Claim 25
Dependent Claim
19 words
The memory array of claim 17, wherein the substrate includes an insulating layer from which the pillar outwardly extends.
Claim 26
Dependent Claim
23 words
The memory array of claim 17, wherein the at least one first source/drain interconnection line is formed at least partially within the substrate.
Claim 27
Dependent Claim
13 words
The memory array of claim 17, wherein the gate lines are substantially parallel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-09 | 2003-02-08 | 2003-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-09 | 2007-02-08 | 2007-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-09 | 2011-02-08 | 2011-08-10 | $7700.00 | Window Closed / Lapsed |