US5907170A — Circuit and method for an open bit line memory ce…

Claim 1

Independent Claim 120 words

A memory cell, comprising: an access transistor formed in a pillar of single crystal semiconductor material, the transistor having first and second source/drain regions and a body region that are vertically aligned; a body contact coupled to the body region; a gate disposed on a side of the pillar, opposite from the body contact; a trench capacitor, wherein the trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide; and an insulator layer that separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.

Claim 2

Dependent Claim 120 words

A memory cell, comprising: an access transistor formed in a pillar of single crystal semiconductor material, the transistor having first and second source/drain regions and a body region that are vertically aligned; a body contact coupled to the body region; a gate disposed on a side of the pillar, opposite from the body contact; a trench capacitor, wherein the trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide; and an insulator layer that separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.

Claim 3

Dependent Claim 20 words

The memory cell of claim 1, wherein the second plate of the trench capacitor surrounds the second source drain region.

Claim 4

Dependent Claim 12 words

The memory cell of claim 1, wherein the second plate comprises polysilicon.

Claim 5

Dependent Claim 27 words

The memory cell of claim 1, and further comprising an ohmic contact that couples the second plate to a layer of semiconductor material through the insulator layer.

Claim 6

Dependent Claim 233 words

A memory device, comprising: an array of memory cells, each cell including a vertical access transistor formed of a semiconductor pillar that extends outwardly from an insulator layer on a substrate with body and first and second source/drain regions, a gate disposed adjacent to a side of the pillar adjacent to the body region, and a trench capacitor wherein a first plate of the trench capacitor is integral with the first source/drain region and a second plate of the capacitor is disposed adjacent to the first plate; a number of bit lines that are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor so as to form columns of memory cells; a number of word lines, each word line disposed orthogonally to the bit lines in a trench between rows of the memory cells for addressing gates of the access transistors of the memory cells that are adjacent to the word line; a number of body lines, each body line disposed in a trench between rows of memory cells so as to contact the body regions of access transistors on a side of the trench opposite the word line in the trench; and a row decoder coupled to the word lines and body lines and a column decoder coupled to the bit lines so as to selectively access the cells of the array.

Claim 7

Dependent Claim 233 words

A memory device, comprising: an array of memory cells, each cell including a vertical access transistor formed of a semiconductor pillar that extends outwardly from an insulator layer on a substrate with body and first and second source/drain regions, a gate disposed adjacent to a side of the pillar adjacent to the body region, and a trench capacitor wherein a first plate of the trench capacitor is integral with the first source/drain region and a second plate of the capacitor is disposed adjacent to the first plate; a number of bit lines that are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor so as to form columns of memory cells; a number of word lines, each word line disposed orthogonally to the bit lines in a trench between rows of the memory cells for addressing gates of the access transistors of the memory cells that are adjacent to the word line; a number of body lines, each body line disposed in a trench between rows of memory cells so as to contact the body regions of access transistors on a side of the trench opposite the word line in the trench; and a row decoder coupled to the word lines and body lines and a column decoder coupled to the bit lines so as to selectively access the cells of the array.

Claim 8

Dependent Claim 12 words

The memory device of claim 5, wherein the body lines comprise polysilicon.

Claim 9

Dependent Claim 36 words

The memory device of claim 5, wherein a surface area of the memory cell is substantially 4F 2 , where F is a minimum feature size for the lithographic process used to form the memory cell.

Claim 10

Dependent Claim 23 words

The memory device of claim 5, wherein the second plate of the trench capacitor surrounds the second source/drain region of the access transistor.

Claim 11

Dependent Claim 20 words

The memory device of claim 5, wherein the second plate of the trench capacitor is maintained at approximately ground potential.

Claim 12

Dependent Claim 23 words

The memory device of claim 5, wherein the second plate of the trench capacitor comprises polysilicon that is maintained at a constant potential.

Claim 13

Dependent Claim 12 words

The memory device of claim 5, wherein the word lines are sub-lithographic.

Claim 14

Dependent Claim 157 words

A memory array comprising: an array of memory cells, each memory cell including an access transistor having body and first and second source/drain regions vertically formed outwardly from an insulator layer on a substrate in a single crystalline semiconductor pillar and a gate disposed adjacent to a side of the transistor, the second source/drain region including an upper semiconductor surface; a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells; a number of body address lines interconnecting body regions of selected access transistors in the rows of memory cells; a number of first isolation trenches separating adjacent rows of memory cells, each isolation trench housing a word line and a body address line; and a number of second isolation trenches, each substantially orthogonal to the first isolation trenches and interposed between adjacent memory cells so as to form a number of columns of the array.

Claim 15

Dependent Claim 157 words

A memory array comprising: an array of memory cells, each memory cell including an access transistor having body and first and second source/drain regions vertically formed outwardly from an insulator layer on a substrate in a single crystalline semiconductor pillar and a gate disposed adjacent to a side of the transistor, the second source/drain region including an upper semiconductor surface; a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells; a number of body address lines interconnecting body regions of selected access transistors in the rows of memory cells; a number of first isolation trenches separating adjacent rows of memory cells, each isolation trench housing a word line and a body address line; and a number of second isolation trenches, each substantially orthogonal to the first isolation trenches and interposed between adjacent memory cells so as to form a number of columns of the array.

Claim 16

Dependent Claim 23 words

The memory array of claim 12, wherein the gates of the access transistors are each formed integral with one of the word lines.

Claim 17

Dependent Claim 30 words

The memory array of claim 12, wherein a surface area of the memory cell is 4F 2 , where F is a minimum feature size for the lithographic process used.

Claim 18

Dependent Claim 23 words

The memory array of claim 12, wherein the second plate of the trench capacitor surrounds the second source/drain region of the access transistor.

Claim 19

Dependent Claim 17 words

The memory array of claim 12, wherein the second plate of the body address lines comprise polysilicon.

Claim 20

Dependent Claim 26 words

The memory array of claim 12, wherein the word lines have a width that is less than the minimum feature size, F, of the lithographic process.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-05-24	2002-11-23	2003-05-25	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-05-24	2006-11-23	2007-05-25	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-05-24	2010-11-23	2011-05-25	$7700.00	Window Closed / Lapsed

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

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