US6043527A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
Assignee: Micron Technology Inc
•
Filing: 1998-04-14
•
Granted: 2000-03-28
•
Expires: 2018-04-14
Abstract
Abstract A memory device is described which has an n-channel field effect transistor coupled between a memory cell and a data communication line. An NPN bipolar junction transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar junction transistor is described as coupled to a body of the n-channel access transistor. During operation the n-channel field effect transistor is used for writing data to a memory cell, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:17
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/405; H; H10; H10B; H10B12/00; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10B12/30; H10B12/39; H10B12/395
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
94 words
A memory cell access device comprising: an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line; and an NPN bipolar junction transistor coupled between the trench plate trench capacitor and the data communication line, wherein the NPN bipolar junction transistor provides a current transfer path during read operations, and is cooperatively coupled such that the n-channel transistor and the NPN bipolar junction transistor are connected in parallel, a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
Claim 2
Dependent Claim
94 words
A memory cell access device comprising: an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line; and an NPN bipolar junction transistor coupled between the trench plate trench capacitor and the data communication line, wherein the NPN bipolar junction transistor provides a current transfer path during read operations, and is cooperatively coupled such that the n-channel transistor and the NPN bipolar junction transistor are connected in parallel, a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
Claim 3
Dependent Claim
26 words
The memory cell access device of claim 1, wherein the n-channel field effect transistor and the NPN bipolar junction transistor are fabricated as a single unit.
Claim 4
Dependent Claim
94 words
The memory cell access device of claim 2, wherein the single unit comprises: a first layer of n-type semiconductor material; a p-type semiconductor material fabricated outwardly from the first layer of n-type semiconductor material; a gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation; and a second layer of n-type semiconductor material fabricated on top of the p-type semiconductor material, such that the p-type semiconductor material functions as both a body of the n-channel field effect transistor and a base of the NPN bipolar junction transistor.
Claim 5
Dependent Claim
40 words
The memory cell access device of claim 3, wherein the p-type semiconductor material has a doping profile such that a top portion of the p-type semiconductor material is more heavily doped than a bottom portion of the p-type semiconductor material.
Claim 6
Dependent Claim
28 words
The memory cell access device of claim 3, wherein a portion of the first layer of n-type material functions as one plate of the trench plate trench capacitor.
Claim 7
Dependent Claim
45 words
The memory cell access device of claim 5, wherein the portion of the first layer of n-type material that functions as one plate of the trench capacitor is surrounded by a polysilicon mesh that functions as the second plate of the trench plate trench capacitor.
Claim 8
Dependent Claim
106 words
A memory cell access device comprising: an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line; an NPN bipolar junction transistor coupled between the trench plate trench capacitor and the data communication line, such that the n-channel transistor and the NPN bipolar junction transistor are connected in parallel, a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor; and wherein the n-channel field effect transistor is used to write date to the memory cell, and the NPN bipolar junction transistor is used to read data from the memory cell.
Claim 9
Dependent Claim
106 words
A memory cell access device comprising: an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line; an NPN bipolar junction transistor coupled between the trench plate trench capacitor and the data communication line, such that the n-channel transistor and the NPN bipolar junction transistor are connected in parallel, a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor; and wherein the n-channel field effect transistor is used to write date to the memory cell, and the NPN bipolar junction transistor is used to read data from the memory cell.
Claim 10
Dependent Claim
102 words
A low voltage memory cell access device fabricated as a vertical pillar structure, the memory cell access device comprising: a field effect transistor coupled between a trench plate trench capacitor and a data communication line; and a bipolar junction transistor coupled between the trench plate trench capacitor and the data communication line, wherein the bipolar junction transistor provides a current transfer path during read operations, and is cooperatively coupled such that the field effect transistor and the bipolar junction transistor are connected in parallel, a base connection of the bipolar junction transistor is coupled to a body of the field effect transistor.
Claim 11
Dependent Claim
102 words
A low voltage memory cell access device fabricated as a vertical pillar structure, the memory cell access device comprising: a field effect transistor coupled between a trench plate trench capacitor and a data communication line; and a bipolar junction transistor coupled between the trench plate trench capacitor and the data communication line, wherein the bipolar junction transistor provides a current transfer path during read operations, and is cooperatively coupled such that the field effect transistor and the bipolar junction transistor are connected in parallel, a base connection of the bipolar junction transistor is coupled to a body of the field effect transistor.
Claim 12
Dependent Claim
28 words
The low voltage memory cell access device of claim 8 wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
Claim 13
Dependent Claim
124 words
The low voltage memory cell access device of claim 9 wherein the field effect transistor and the bipolar junction transistor are fabricated as a common structure comprising: a first layer of n-type semiconductor material; a p-type semiconductor material fabricated on top of the first layer of n-type semiconductor material; a gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation; a second layer of n-type semiconductor material fabricated outwardly from the p-type semiconductor material, such that the p-type semiconductor material functions as both a body of the n-channel field effect transistor and a base of the NPN bipolar junction transistor; and a base contact formed adjacent to the p-type semiconductor material on a side opposite the gate.
Claim 14
Dependent Claim
33 words
The low voltage memory cell access device of claim 10, wherein the first layer of n-type semiconductor material includes a portion that functions as a first plate of the trench plate trench capacitor.
Claim 15
Dependent Claim
43 words
The low voltage memory cell access device of claim 10, and further comprising a first word line coupled to the gate for activating the n-channel transistor, and a second word line coupled to the base contact for activating the NPN bipolar junction transistor.
Claim 16
Dependent Claim
42 words
The low voltage memory cell access device of claim 8, wherein the p-type semiconductor material has a doping profile such that a top portion of the p-type semiconductor material is more heavily doped than a bottom portion of the p-type semiconductor material.
Claim 17
Dependent Claim
25 words
The low voltage memory cell access device of claim 8, wherein the low voltage memory cell access device is fabricated using a silicon-on-insulator (SOI) construction.
Claim 18
Dependent Claim
23 words
The low voltage memory cell access device of claim 8, wherein the low voltage memory cell access device is fabricated in bulk silicon.
Claim 19
Dependent Claim
131 words
A memory device having a low voltage supply, the memory device comprising: a plurality of memory cells; a plurality of data communication bit lines; a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines, each of the plurality of memory cell access devices comprising: a field effect transistor, and a bipolar junction transistor, such that the field effect transistor and the bipolar junction access transistor are connected in parallel between the trench plate trench capacitor and a data communication bit line, and a current sense amplifier coupled to the plurality of data communication bit lines, wherein the current sense amplifier detects current signals provided to the data communication bit lines by the bipolar junction transistor during a read operation.
Claim 20
Dependent Claim
131 words
A memory device having a low voltage supply, the memory device comprising: a plurality of memory cells; a plurality of data communication bit lines; a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines, each of the plurality of memory cell access devices comprising: a field effect transistor, and a bipolar junction transistor, such that the field effect transistor and the bipolar junction access transistor are connected in parallel between the trench plate trench capacitor and a data communication bit line, and a current sense amplifier coupled to the plurality of data communication bit lines, wherein the current sense amplifier detects current signals provided to the data communication bit lines by the bipolar junction transistor during a read operation.
Claim 21
Dependent Claim
30 words
The memory device of claim 16, wherein each memory cell access device includes a field effect transistor and a bipolar junction transistor that share a common pillar of semiconductor material.
Claim 22
Dependent Claim
17 words
The memory device of claim 16 wherein the memory device is a dynamic random access memory (DRAM).
Claim 23
Dependent Claim
24 words
The memory device of claim 16 wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
References Cited (Backward Citations)
US3931617A
Cited
US4051354A
Cited
US4604162A
Cited
US5208657A
Cited
US4761768A
Cited
US4766569A
Cited
US5102817A
Cited
US4673962A
Cited
US4677589A
Cited
US4663831A
Cited
JPS6366963A
Cited
US5017504A
Cited
US5427972A
Cited
US5001526A
Cited
US5072269A
Cited
US5057896A
Cited
US4958318A
Cited
US4920065A
Cited
US5327380A
Cited
US5327380B1
Cited
US5021355A
Cited
US5028977A
Cited
US5316962A
Cited
US5006909A
Cited
US5410169A
Cited
US5216266A
Cited
US5177576A
Cited
US4987089A
Cited
US5223081A
Cited
US5110752A
Cited
US5341331A
Cited
US5202278A
Cited
US5376575A
Cited
US5504357A
Cited
US5177028A
Cited
US5329481A
Cited
US5156987A
Cited
US5528062A
Cited
US5466625A
Cited
US5320880A
Cited
US5266514A
Cited
US5422499A
Cited
US5391911A
Cited
US5438009A
Cited
US5616934A
Cited
US5519236A
Cited
US5392245A
Cited
US5644540A
Cited
US5445986A
Cited
US5460316A
Cited
US5483094A
Cited
US5393704A
Cited
US5396093A
Cited
US5492853A
Cited
US5574299A
Cited
US5414287A
Cited
US5460988A
Cited
US5495441A
Cited
US5432739A
Cited
US5563083A
Cited
US5483487A
Cited
US5440158A
Cited
US5834814A
Cited
US5705415A
Cited
US5593912A
Cited
US5508542A
Cited
US5646900A
Cited
US5497017A
Cited
US5508219A
Cited
US5640342A
Cited
US5691230A
Cited
US5907170A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-28 | 2003-09-27 | 2004-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-28 | 2007-09-27 | 2008-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-28 | 2011-09-27 | 2012-03-28 | $7700.00 | Window Closed / Lapsed |