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US5329481A
Expired / Lapsed
US
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Semiconductor device having a memory cell
Assignee: US Philips Corp
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Filing: 1992-12-14
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Granted: 1994-07-12
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Expires: 2012-12-14
Abstract
Abstract A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T 1 ) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T 2 ). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T 5 ).
Inventors
- 👤 Evert Seevinck
- 👤 Maarten Vertregt
- 👤 Godefridus A. M. Hurkx
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:34
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H10B; H10B12/00; H10B12/10; H10B69/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
132 words
A semiconductor device comprising a semiconductor body provided with a programmable memory cell which comprises a bipolar transistor with an emitter and a collector of a first conductivity type mutually separated by a base of a second, opposite conductivity type, the emitter and the collector being coupled to a first and a second supply line, respectively, and the base being coupled to writing means through at least a control transistor provided with a control electrode, characterized in that the memory cell is coupled to reading means which are included in a current path which extends between the first and the second supply line and which comprises a current path between the emitter and the collector of the bipolar transistor, the reading means being connected between the emitter and the first supply line.
Claim 2
Dependent Claim
132 words
A semiconductor device comprising a semiconductor body provided with a programmable memory cell which comprises a bipolar transistor with an emitter and a collector of a first conductivity type mutually separated by a base of a second, opposite conductivity type, the emitter and the collector being coupled to a first and a second supply line, respectively, and the base being coupled to writing means through at least a control transistor provided with a control electrode, characterized in that the memory cell is coupled to reading means which are included in a current path which extends between the first and the second supply line and which comprises a current path between the emitter and the collector of the bipolar transistor, the reading means being connected between the emitter and the first supply line.
Claim 3
Dependent Claim
47 words
A semiconductor device as claimed in claim 1, characterized in that the collector is coupled to the second supply line through a switchable load, and in that the load is provided with switching means for switching the load between a comparatively high and a comparatively low value.
Claim 4
Dependent Claim
48 words
A semiconductor device as claimed in claim 2, characterized in that the switchable load comprises a field effect transistor having a source and a drain between which the electric conductivity is controllable by means of a gate electrode, and in that the gate electrode forms the switching means.
Claim 5
Dependent Claim
124 words
A semiconductor device as claimed in claim 2, characterized in that the device comprises, in addition to the memory cell, a number of similar further memory cells, which memory cells are organized in a memory matrix comprising rows and columns, in that the collectors of the cells within a row are coupled to the second supply line through a common load, in that the switching means of the common load of a row of memory cells are coupled to a first read selection line, in that the emitters of the memory cells within a column are coupled to a second read selection line, and in that the read selection line is coupled to reading means which are common to a column of memory cells.
Claim 6
Dependent Claim
70 words
A semiconductor device as claimed in claim 4, characterized in that the memory matrix comprises separate write selection lines, in that the control electrodes of the control transistors within a row of memory cells are coupled to a first write selection line, and in that the bases of the memory cells within a column of memory cells are coupled to a second write selection line and to common writing means.
Claim 7
Dependent Claim
32 words
A semiconductor device as claimed in claim 5, characterized in that the second read selection line has a feedback line to the second write selection line within a column of memory cells.
References Cited (Backward Citations)
US4090254A
Cited
US5060194A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |