US4677589A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory cell having a charge amplifier
Assignee: Advanced Micro Devices Inc
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Filing: 1985-07-26
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Granted: 1987-06-30
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Expires: 2005-07-26
Abstract
Abstract An improved dynamic random access memory (DRAM) cell circuit (46) having a charge amplifier is presented. The improvement comprises a bipolar amplification means (64) for amplifying a charge as it is read out of the memory cell (46). According to one embodiment of the present invention, in addition to a standard charge storage capacitor (50) and MOS transistor (48), the memory cell (46) also includes a write control line (60) and a second MOS transistor (62) for writing a "1" bit of information into the memory cell (46). These improvements require little or no additional space when used in a DRAM circuit and allow a reduction in the required capacitor area.
Inventors
- 👤 Jacob D. Haskell
- 👤 Craig S. Sander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/405
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
194 words
An improved memory cell for a dynamic random access memory (DRAM) circuit having first and second reference potential terminals, a word line, a bit line, a capacitor, a first MOS transistor having a first terminal coupled at a charge storage node to a first terminal of said capacitor, said first MOS transistor also having a gate terminal coupled to said word line, the improvement comprising: write control means, having: a write control line, and an MOS switching means having a first terminal coupled to said first reference potential terminal, a second terminal coupled to said write control line and further coupled to a second terminal of said capacitor, said MOS switching means also having a third terminal coupled at said charge storage node to said first terminal of said capacitor, and to said first terminal of said first MOS transistor; and a bipolar amplification means having a first terminal coupled to a second terminal of said first MOS transistor, a second terminal coupled to said second reference potential terminal and a third terminal coupled to said bit line, such that a charge amplified by said bipolar amplification means is received on said bit line.
Claim 2
Dependent Claim
194 words
An improved memory cell for a dynamic random access memory (DRAM) circuit having first and second reference potential terminals, a word line, a bit line, a capacitor, a first MOS transistor having a first terminal coupled at a charge storage node to a first terminal of said capacitor, said first MOS transistor also having a gate terminal coupled to said word line, the improvement comprising: write control means, having: a write control line, and an MOS switching means having a first terminal coupled to said first reference potential terminal, a second terminal coupled to said write control line and further coupled to a second terminal of said capacitor, said MOS switching means also having a third terminal coupled at said charge storage node to said first terminal of said capacitor, and to said first terminal of said first MOS transistor; and a bipolar amplification means having a first terminal coupled to a second terminal of said first MOS transistor, a second terminal coupled to said second reference potential terminal and a third terminal coupled to said bit line, such that a charge amplified by said bipolar amplification means is received on said bit line.
Claim 3
Dependent Claim
18 words
A memory cell in accordance with claim 1, wherein said MOS switching means comprises a second MOS transistor.
Claim 4
Dependent Claim
45 words
A memory cell in accordance with claim 2, wherein said bipolar amplification means comprises a bipolar transistor, and said first, second and third terminals of the bipolar amplification means comprise, respectively, a base terminal, a collector terminal, and an emitter terminal of the bipolar transistor.
Claim 5
Dependent Claim
30 words
A memory cell in accordance with claim 3, wherein said first and second MOS transistors each comprises a p-channel MOS transistor and said bipolar transistor comprises an n-p-n bipolar transistor.
Claim 6
Dependent Claim
30 words
A memory cell in accordance with claim 3, wherein said first and second MOS transistors each comprises an n-channel MOS transistor and said bipolar transistor comprises a p-n-p bipolar transistor.
Claim 7
Dependent Claim
255 words
In a dynamic random access memory (DRAM) circuit, a memory cell comprising: a first MOS transistor having first and second source/drain terminals and a gate terminal, said first source/drain terminal being coupled to a first reference potential terminal of said DRAM circuit; a capacitor for storing a charge, said capacitor having a first terminal coupled to said gate terminal of said first MOS transistor, and a second terminal coupled to said second source/drain terminal of said MOS transistor; a write control line for writing a "1" bit of information into said memory cell, said write control line being coupled at a first common node to said first terminal of said capacitor and to said gate terminal of said first MOS transistor; a second MOS transistor having first and second source/drain terminals and a gate terminal, said first source/drain terminal of said second MOS transistor being coupled at a second common node to said second terminal of said capacitor and to said second source/drain terminal of said first MOS transistor, and said gate terminal of said second MOS transistor being coupled to a word line of said DRAM circuit; and a bipolar transistor having a base terminal coupled to said second source/drain terminal of said second MOS transistor, a collector terminal coupled to a second reference potential terminal of said DRAM circuit, and an emitter terminal coupled to a bit line of said DRAM circuit, such that said bipolar transistor operates to amplify a charge being read out of said memory cell onto said bit line.
Claim 8
Dependent Claim
255 words
In a dynamic random access memory (DRAM) circuit, a memory cell comprising: a first MOS transistor having first and second source/drain terminals and a gate terminal, said first source/drain terminal being coupled to a first reference potential terminal of said DRAM circuit; a capacitor for storing a charge, said capacitor having a first terminal coupled to said gate terminal of said first MOS transistor, and a second terminal coupled to said second source/drain terminal of said MOS transistor; a write control line for writing a "1" bit of information into said memory cell, said write control line being coupled at a first common node to said first terminal of said capacitor and to said gate terminal of said first MOS transistor; a second MOS transistor having first and second source/drain terminals and a gate terminal, said first source/drain terminal of said second MOS transistor being coupled at a second common node to said second terminal of said capacitor and to said second source/drain terminal of said first MOS transistor, and said gate terminal of said second MOS transistor being coupled to a word line of said DRAM circuit; and a bipolar transistor having a base terminal coupled to said second source/drain terminal of said second MOS transistor, a collector terminal coupled to a second reference potential terminal of said DRAM circuit, and an emitter terminal coupled to a bit line of said DRAM circuit, such that said bipolar transistor operates to amplify a charge being read out of said memory cell onto said bit line.
References Cited (Backward Citations)
US3745539A
Cited
US4168536A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-29 | 1990-12-29 | 1991-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-29 | 1994-12-29 | 1995-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-29 | 1998-12-29 | 1999-06-30 | $7700.00 | Window Closed / Lapsed |