US4168536A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Capacitor memory with an amplified cell signal
Assignee: International Business Machines Corp
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Filing: 1977-06-30
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Granted: 1979-09-18
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Expires: 1997-06-30
Abstract
Abstract A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.
Inventors
- 👤 Madhukar L. Joshi
- 👤 Wilbur D. Pricer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
76 words
A memory cell circuit comprising a data line, a series circuit including interconnected switching means, charge storage means and a resistor coupled between said data line and a point of reference potential, an amplifier having an input connected to said resistor of said series circuit at a point between said resistor and said charge storage means and an output coupled to said data line, and a selection line coupled so as to operate said switching means.
Claim 2
Dependent Claim
76 words
A memory cell circuit comprising a data line, a series circuit including interconnected switching means, charge storage means and a resistor coupled between said data line and a point of reference potential, an amplifier having an input connected to said resistor of said series circuit at a point between said resistor and said charge storage means and an output coupled to said data line, and a selection line coupled so as to operate said switching means.
Claim 3
Dependent Claim
25 words
A memory cell circuit as set forth in claim 1 wherein said switching means and said amplifier are first and second field effect transistors, respectively.
Claim 4
Dependent Claim
26 words
A memory cell circuit as set forth in claim 1 wherein the output of said amplifier is coupled to said data line through said switching means.
Claim 5
Dependent Claim
23 words
A memory cell circuit as set forth in claim 1 wherein the output of said amplifier is connected directly to said data line.
Claim 6
Dependent Claim
24 words
A memory cell circuit as set forth in claim 1 wherein said charge storage means is interposed between said switching means and said resistor.
Claim 7
Dependent Claim
33 words
A memory cell circuit as set forth in claim 5 wherein said amplifier is coupled between said data line and a second point of reference potential having a magnitude greater than zero volts.
Claim 8
Dependent Claim
38 words
A memory cell circuit as set forth in claim 6 wherein the point of reference potential to which said series circuit is coupled and the point of reference potential to which said amplifier is coupled have differing potentials.
Claim 9
Dependent Claim
31 words
A memory cell circuit as set forth in claim 1 wherein said point of reference potential has a voltage magnitude capable of providing a full charge to said charge storage means.
Claim 10
Dependent Claim
26 words
A memory cell circuit as set forth in claim 8 wherein said charge storage means is interposed between said point of reference potential and said resistor.
Claim 11
Dependent Claim
32 words
A memory cell circuit as set forth in claim 9 wherein said charge storage means is a capacitor, and said switching means and said amplifier are first and second field effect transistors.
Claim 12
Dependent Claim
47 words
A memory cell circuit as set forth in claim 10 wherein the output of said amplifier is connected to the common point between said first transistor and said resistor and the input of said amplifier is connected to the common point between said resistor and said capacitor.
Claim 13
Dependent Claim
25 words
A memory cell circuit a set forth in claim 1 wherein said charge storage means is disposed between said switching means and said data line.
Claim 14
Dependent Claim
23 words
A memory cell circuit as set forth in claim 12 wherein the output of said amplifier is connected directly to said data line.
Claim 15
Dependent Claim
73 words
A memory cell circuit comprising a bit/sense line, a series circuit including charge storage means and resistive means, means for selectively coupling said series circuit to said bit/sense line, and means having an input connected to said resistive means of said series circuit at a point between said resistive means and said charge storage means for amplifying the signal on said charge storage means and having an output coupled to said bit/sense line.
Claim 16
Dependent Claim
73 words
A memory cell circuit comprising a bit/sense line, a series circuit including charge storage means and resistive means, means for selectively coupling said series circuit to said bit/sense line, and means having an input connected to said resistive means of said series circuit at a point between said resistive means and said charge storage means for amplifying the signal on said charge storage means and having an output coupled to said bit/sense line.
Claim 17
Dependent Claim
30 words
A memory cell circuit as set forth in claim 14 wherein said selectively coupling means includes a transistor and a word line coupled to a control electrode of said transistor.
Claim 18
Dependent Claim
18 words
A memory cell circuit as set forth in claim 14 wherein said charge storage means is a capacitor.
Claim 19
Dependent Claim
41 words
A memory cell circuit as set forth in claim 16 wherein said means for amplifying includes a field effect transistor having a gate electrode coupled to said charge storage means at the common point between said capacitor and said resistive means.
Claim 20
Dependent Claim
29 words
A memory cell circuit as set forth in claim 14 wherein said means for amplifying includes a field effect transistor having a gate electrode coupled to said resistive means.
References Cited (Backward Citations)
US3652914A
Cited
DE2456893A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-09-17 | 1983-03-19 | 1983-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-09-17 | 1987-03-19 | 1987-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-09-17 | 1991-03-19 | 1991-09-18 | $7700.00 | Window Closed / Lapsed |