Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array

Abstract

Abstract A densely packed array of vertical semiconductor devices, having pillars and deep trench capacitors, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of all the cells are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F 2 to be maintained The array is suitable for Gbit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.

Inventors

• 👤 Stuart Mcallister Burns, Jr.
• 👤 Hussein Ibrahim Hanafi
• 👤 Howard Leo Kalter
• 👤 Jeffrey J. Welser
• 👤 Waldemar Walter Kocon

Bibliographic Details