US4796228A
Expired / Lapsed
US
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Erasable electrically programmable read only memory cell using trench edge tunnelling
Assignee: Texas Instruments Inc
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Filing: 1986-06-02
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Granted: 1989-01-03
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Expires: 2006-06-02
Abstract
Abstract An electrically programmable read only memory cell formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate. The trench has bottom corners sufficiently sharp so as to enhance the likelihood of tunnelling between corner regions of the trench and the floating gate over that between planar surface regions of the trench and floating gate.
Inventors
- 👤 David A. Baglee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:29
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
75 words
An electrically programmable read only memory cell formed in a face of a semiconductor substrate, comprising a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in said substrate wherein said trench has edges sufficiently sharp so as to enhance the likelihood of tunneling between corner regions of said trench and said floating gate over that between planar surface regions of said trench and floating gate.
Claim 2
Dependent Claim
75 words
An electrically programmable read only memory cell formed in a face of a semiconductor substrate, comprising a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in said substrate wherein said trench has edges sufficiently sharp so as to enhance the likelihood of tunneling between corner regions of said trench and said floating gate over that between planar surface regions of said trench and floating gate.
Claim 3
Dependent Claim
19 words
A cell according to claim 1, wherein said substrate is silicon and said floating and control gates are polysilicon.
Claim 4
Dependent Claim
48 words
A cell according to claim 1, including a tunnel device coupled to a source of said floating gate transistor and having a floating gate connected to the floating gate of said floating gate transistor and a control gate connected to the control gate of said floating gate transistor.
Claim 5
Dependent Claim
21 words
A cell according to claim 1, including a selection transistor formed in said substrate in series with said floating gate transistor.
Claim 6
Dependent Claim
16 words
A cell according to claim 1, wherein walls and a bottom of said trench are rectangular.
Claim 7
Dependent Claim
25 words
A cell according to claim 2, wherein said substrate is P-type silicon, said and the thickness of said polysilicon gates are each about 0.4 microns.
Claim 8
Dependent Claim
13 words
A device according to claim 2, wherein said polysilicon layers are conformally deposited.
Claim 9
Dependent Claim
20 words
A cell according to claim 1, including a common moat region on at least two opposed ends of said trench.
Claim 10
Dependent Claim
36 words
A cell according to claim 5, wherein said trench has a width in the range of about 2 to 5 microns, a length of 2 to 5 microns and a depth of 1 to 3 microns.
Claim 11
Dependent Claim
27 words
A cell according to claim 2, including a silicon dioxide region between said substrate and said floating gate having a thickness of approximately 250 to 350 Angstroms.
Claim 12
Dependent Claim
12 words
A cell according to claim 1, wherein said cell is electrically erasable.
Claim 13
Dependent Claim
85 words
An electrically erasable programmable read only memory cell formed in a face of a semiconductor body, comprising: a floating gate transistor having both a floating gate and a control gate formed at least partially in a trench in said body with a channel region extending around said trench, said trench having bottom edges sufficiently sharp so that with a programming voltage applied between said channel region and said control gate electron tunnelling occurs between said channel region and said floating gate proximate said edge regions.
Claim 14
Dependent Claim
85 words
An electrically erasable programmable read only memory cell formed in a face of a semiconductor body, comprising: a floating gate transistor having both a floating gate and a control gate formed at least partially in a trench in said body with a channel region extending around said trench, said trench having bottom edges sufficiently sharp so that with a programming voltage applied between said channel region and said control gate electron tunnelling occurs between said channel region and said floating gate proximate said edge regions.
Claim 15
Dependent Claim
21 words
A cell according to claim 12, wherein said programming voltage is in the range of approximately 10 volts to 28 volts.
Claim 16
Dependent Claim
53 words
A cell according to claim 12, wherein said trench is surrounded by a diffused moat region of a first conductivity type and has a difficult channel region of the first conductivity type extending around sides and a bottom of said trench from the moat one side to the moat on another opposite side.
Claim 17
Dependent Claim
29 words
A cell according to claim 14, wherein said semiconductor body is silicon, said floating gate and control gates are doped polysilicon and said moat and channel regions are N-type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-03 | 1992-07-04 | 1993-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-03 | 1996-07-04 | 1997-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-03 | 2000-07-04 | 2001-01-03 | $7700.00 | Window Closed / Lapsed |