US4695979A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Modified four transistor EEPROM cell
Assignee: Texas Instruments Inc
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Filing: 1985-09-09
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Granted: 1987-09-22
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Expires: 2005-09-09
Abstract
Abstract An electrically erasable programmable memory cell of the four transistor type in which a floating gate transistor has one end of its source to drain path coupled to the write line and the other end to the read line through a read switch. Its control gate is connected to the sense line. A tunnel device has a cathode connected to the floating gate of the floating gate transistor, and an anode through a write switch connected to the write line. The gates of both the read and write select transistors are connected to the row line. By coupling one end of the read switch to the read line rather than connecting one end of the source to drain path of the floating gate transistor to the read line for unselected cells in which the read switch is off, only the capacitance of one end of the read switch is added to the parasitic capacitance of the read line whether the floating gate of the floating gate transistor has previously been charged negatively or positively. Thus, the precharging time of the read line will be independent of the programmed condition of the cell and will result in an access time that is as fast or faster for either programmed condition than previously attainable.
Inventors
- 👤 James A. Tuvell
- 👤 Michael C. Smayling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:36
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
228 words
An electrically erasable programmable memory cell of a type having interconnected transistors coupled to a conducting read, write, sense and row line, comprising: a floating gate transistor having a control gate, connected to said sense line, a source to drain conducting path and a floating gate; a tunnel device having a cathode coupled to the floating gate, an anode, and a tunnel control electrode coupled to the sense line; read switch means for providing a conducting path between said read line and one end of the source to drain path of said floating gate transistor in response to the voltage on said row line exceeding a selective threshold value and for opening the conductive path when the row line voltage falls below the selective threshold value; write switch means for providing a conductive path between said write line and the anode of said tunnel device in response to the voltage on said row line exceeding a write selective value and for opening the conductive path when the row line voltage falls below the write selective value; wherein another end of the source to drain path of said floating gate transistor is connected to said write line and said tunnel device is operative in response to a voltage between said sense line and said write line exceeding a tunnel threshold value to tunnel electrons to or from said cathode.
Claim 2
Dependent Claim
228 words
An electrically erasable programmable memory cell of a type having interconnected transistors coupled to a conducting read, write, sense and row line, comprising: a floating gate transistor having a control gate, connected to said sense line, a source to drain conducting path and a floating gate; a tunnel device having a cathode coupled to the floating gate, an anode, and a tunnel control electrode coupled to the sense line; read switch means for providing a conducting path between said read line and one end of the source to drain path of said floating gate transistor in response to the voltage on said row line exceeding a selective threshold value and for opening the conductive path when the row line voltage falls below the selective threshold value; write switch means for providing a conductive path between said write line and the anode of said tunnel device in response to the voltage on said row line exceeding a write selective value and for opening the conductive path when the row line voltage falls below the write selective value; wherein another end of the source to drain path of said floating gate transistor is connected to said write line and said tunnel device is operative in response to a voltage between said sense line and said write line exceeding a tunnel threshold value to tunnel electrons to or from said cathode.
Claim 3
Dependent Claim
49 words
A memory cell according to claim 1, wherein said tunnel control electrode is a tunnel control gate connected to said sense line and, in response to the voltage from the gate to anode of said tunnel device exceeding a tunnel threshold value, electrons tunnel between the cathode and anode.
Claim 4
Dependent Claim
53 words
A memory cell according to claim 1, wherein said read switch means is a read transistor having a gate connected to said row line and a source to drain path coupled at one end to the source to drain path of said floating gate transistor and at another end to said read line.
Claim 5
Dependent Claim
41 words
A memory cell according to claim 3, wherein said write switch means is a write transistor having a source to drain path coupled at one end to the anode of said tunnel device and at another end to said write line.
Claim 6
Dependent Claim
40 words
A memory cell according to claim 4, wherein a drain of said floating gate transistor is connected to a drain of said read transistor and a drain of said write transistor is connected to the anode of said tunnel device.
Claim 7
Dependent Claim
225 words
An electrically erasable programmable memory cell of a type having interconnected transistors coupled to a conducting read, write, sense and row line, comprising; a floating gate transistor having a control gate, connected to said sense line, a source to drain conducting path and a floating gate; a tunnel device having a cathode coupled to the floating gate, an anode, and a tunnel control electrode coupled to the sense line; a read transistor having a source to drain path coupled between the read line and one end of the source to drain path of said floating gate transistor and having a control gate coupled to the row line operative in response to the voltage on said row line exceeding a selective threshold value to become conductive; a write transistor having a source to drain path coupled between the write line and the anode of said tunnel device and having a gate coupled to the row line and operative to conduct in response to the voltage on said row line exceeding a write selective value; wherein another end of the source to drain path of said floating gate transistor is connected to said write line and said tunnel device is operative to tunnel electrons to or from said cathode in response to a voltage between said sense line and said write line exceeding a tunnel threshold value.
Claim 8
Dependent Claim
225 words
An electrically erasable programmable memory cell of a type having interconnected transistors coupled to a conducting read, write, sense and row line, comprising; a floating gate transistor having a control gate, connected to said sense line, a source to drain conducting path and a floating gate; a tunnel device having a cathode coupled to the floating gate, an anode, and a tunnel control electrode coupled to the sense line; a read transistor having a source to drain path coupled between the read line and one end of the source to drain path of said floating gate transistor and having a control gate coupled to the row line operative in response to the voltage on said row line exceeding a selective threshold value to become conductive; a write transistor having a source to drain path coupled between the write line and the anode of said tunnel device and having a gate coupled to the row line and operative to conduct in response to the voltage on said row line exceeding a write selective value; wherein another end of the source to drain path of said floating gate transistor is connected to said write line and said tunnel device is operative to tunnel electrons to or from said cathode in response to a voltage between said sense line and said write line exceeding a tunnel threshold value.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-21 | 1991-03-23 | 1991-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-21 | 1995-03-23 | 1995-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-21 | 1999-03-23 | 1999-09-22 | $7700.00 | Window Closed / Lapsed |