Electrically erasable and programmable semiconductor memory device with trench memory transistor and manufacturing method of the same

Claim 2

An electrically erasable and programmable semiconductor memory device comprising a semiconductor substrate of a first conductivity type having a main surface and parallel trenches defined by lateral sidewalls and floors, and a plurality of pairs of memory cells formed in respective sidewalls of said trenches, said pairs of memory cells spaced and isolated from each other by an isolating and insulating film formed on said main surface of said semiconductor substrate, said device including a control gate layer extending between and into said trenches, each of said plurality of memory cells comprising: a floating gate electrode including an upper portion formed on a respective sidewall of a trench with a first insulating film having a first thickness interposed therebetween, and a lower portion formed on floor of said trench with a second insulating film having a second thickness smaller than said first thickness interposed therebetween; a first impurity region of a second conductivity type formed in said main surface of said semiconductor substrate adjacent to said respective sidewall of said respective trench and said upper portion of said floating gate electrode; a second impurity region of said second conductivity formed in common to pairs of said memory cells in said floor of said trench between said lower portions of said floating gate electrodes of each pair of memory cells; and a gate electrode formed on said floating gate electrode with a third insulating film interposed therebetween.

Claim 3

A semiconductor memory device according to claim 1, wherein said gate electrode and said second impurity region are shared by two adjacent memory cells, and two floating gate electrodes of said two adjacent memory cells are opposed to each other and are formed on sidewalls of said trench, interposing said second impurity region formed on said floor of said trench.

Claim 4

An electrically erasable and programmable semiconductor memory device comprising: a semiconductor substrate of a first conductivity type, having a main surface and trenches defined by side walls and bottom walls; a plurality of memory cells arranged in a matrix form of m rows and n columns, each of said m rows including adjacent pairs of memory cells with the adjacent pairs being isolated from each other by an isolating and insulating form formed on said main surface of said semiconductor substrate; m number of word lines associated with the memory cells in each row; n number of bit lines associated with the memory cells in each column; and a plurality of source lines associated with the memory cells in each column, each of said memory cells comprising: a first gate electrode including a first portion and a second portion, said first portion being formed on a side wall of a trench with a first insulating film having a first thickness interposed therebetween, and said second portion being formed on a bottom wall of said trench with a second insulating film having a second thickness smaller than said first thickness interposed therebetween; a first impurity region of a second conductivity type formed at a portion of said main surface of said semiconductor substrate adjacent to said side wall of said trench and located at the vicinity of said first portion of said first gate electrode; a second impurity region of a second conductivity type formed on said bottom wall of said trench and located at the vicinity of said second portion of said first gate electrode; and a second gate electrode formed on said first gate electrode with a third insulating film interposed therebetween, said first impurity region, said second impurity region and said second gate electrode being connected to a bit line, a source line and a word line, respectively.

Claim 5

An electrically erasable and programmable semiconductor memory device comprising: a semiconductor substrate of a first conductivity type, having a main surface and trenches defined by side walls and bottom walls; a plurality of memory cells arranged in a matrix form of m rows and n columns, each of said m rows including adjacent pairs of memory cells with the adjacent pairs being isolated from each other by an isolating and insulating form formed on said main surface of said semiconductor substrate; m number of word lines associated with the memory cells in each row; n number of bit lines associated with the memory cells in each column; and a plurality of source lines associated with the memory cells in each column, each of said memory cells comprising: a first gate electrode including a first portion and a second portion, said first portion being formed on a side wall of a trench with a first insulating film having a first thickness interposed therebetween, and said second portion being formed on a bottom wall of said trench with a second insulating film having a second thickness smaller than said first thickness interposed therebetween; a first impurity region of a second conductivity type formed at a portion of said main surface of said semiconductor substrate adjacent to said side wall of said trench and located at the vicinity of said first portion of said first gate electrode; a second impurity region of a second conductivity type formed on said bottom wall of said trench and located at the vicinity of said second portion of said first gate electrode; and a second gate electrode formed on said first gate electrode with a third insulating film interposed therebetween, said first impurity region, said second impurity region and said second gate electrode being connected to a bit line, a source line and a word line, respectively.

Claim 6

A semiconductor memory device according to claim 3, wherein said word line includes a conductive layer formed integrally with said second gate electrodes and extending in the row direction so as to interconnect said second gate electrodes.

Claim 7

A semiconductor memory device according to claim 3, wherein said source line includes a conductive layer extending in the column direction and connected to said second impurity region extending in the column direction.

Claim 8

A semiconductor memory device according to claim 3, wherein said bit line includes a conductive layer extending in the column direction to interconnect said first impurity regions.

Claim 9

A semiconductor memory device according to claim 3, wherein said word line is arranged perpendicular to said source line and said bit line.